NDLI: Pre-capturing static pulsed flip-flops

Content Provider	IEEE Xplore Digital Library
Author	Ghadiri, A. Mahmoodi, H.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. Eng., Iran Univ. of Sci. & Technol., Tehran, Iran (Ghadiri, A.)
Abstract	The paper presents pre-capturing static pulsed flip-flops (PCSPFF), which are composed of a pulse generator and a static flip-flop with equal toggling delays. The pre-capturing technique makes PCSPFF faster than other high-performance flip-flops. Power consumption of the PCSPFF is observed to be the lowest among high-performance flip-flops. HSPICE simulation results at a frequency of 400 MHz show that the proposed PCSPFF exhibits power-delay-product reductions of 39.7% and 29%, respectively, compared to the hybrid-latch flip-flop and the conditional-capture flip-flop. Moreover, in practical circuits, the proposed PCSPFF shows power reduction of more than 50% and 32%, respectively, compared to the hybrid-latch flip-flop and conditional-capture flip-flop. A double-edge triggering feature can be added to the proposed flip-flops to reduce the clock frequency by 50%. Using double-edge triggering in the proposed flip-flops, an energy saving of 94% is achieved on the clock distribution network. Incorporating the double-edge triggering technique along with sharing pulse generation among flip-flops presents up to 68% power reduction in an 8-bit counter.
Starting Page	2421
Ending Page	2424
File Size	242803
Page Count	4
File Format	PDF
ISBN	0780388348
DOI	10.1109/ISCAS.2005.1465114
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flip-flops Clocks Delay Pulse generation Energy consumption Frequency Latches Power dissipation Pulse amplifiers Paper technology
Content Type	Text
Resource Type	Article

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