NDLI: Cascaded double-stage configuration for high-performance broadband amplification in CMOS

Content Provider	IEEE Xplore Digital Library
Author	Worapishet, A. Roopkom, I.
Copyright Year	2005
Description	Author affiliation: Mahanakorn Microelectron. Res. Center, Mahanakorn Univ. of Technol., Bangkok, Thailand (Worapishet, A.; Roopkom, I.)
Abstract	A high performance distributed amplifier (DA) based on the cascaded double-stage configuration is presented. Theoretical performance analysis, using three performance vectors - gain, bandwidth, and noise factor - is first conducted for the generalized m-cascaded n-stage DA. The analysis result is then exploited to enable comparison between three specific DA configurations that lend themselves to practice, including the classical DA, the cascaded single-stage DA (CSDA) and the cascaded double-stage DA (CDDA). The superiority of the double-stage configuration as indicated by the theoretical discussion is verified through simulations of gigahertz-range amplifiers with a 15dB gain using a 0.25/spl mu/m 2.5V CMOS process. This shows that the CDDA outperforms the DA and the CSDA by more than a factor of 1.6 and 3.0 respectively.
Starting Page	1606
Ending Page	1609
File Size	279855
Page Count	4
File Format	PDF
ISBN	0780388348
DOI	10.1109/ISCAS.2005.1464910
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Distributed amplifiers Capacitance Performance analysis Bandwidth CMOS process CMOS technology Performance gain Inductors Broadband amplifiers Optical noise
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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