NDLI: Behavioural modeling and simulation of a switched-current phase locked loop

Content Provider	IEEE Xplore Digital Library
Author	Wilson, P. Wilcock, R.
Copyright Year	2005
Description	Author affiliation: Sch. of Electron. & Comput. Sci., Southampton Univ., UK (Wilson, P.; Wilcock, R.)
Abstract	Switched-current (SI) methods can provide an effective route to the implementation of analog IC functionality using a standard digital CMOS process. Further, adopting an SI architecture can lead to equivalent performance but with a significantly reduced area compared to switched capacitor structures. The use of behavioural modeling and simulation at a structural and building block level has allowed architectural exploration and evaluation to be carried out on novel topologies based on this approach. The result is an integrated design flow that uses behavioural models to test the performance of the circuit, leading directly to a synthesized structural model that can be verified using a common design platform. This has the obvious benefit of reducing the full custom analog design effort required when developing topologies and building blocks for new processes. We describe the design approach for a phase locked loop (PLL) based on a novel SI architecture using behavioural models written in VHDL-AMS. Simulations demonstrate the performance of the design at a high level and are used to optimize the behaviour of the loop response with regard to design specifications. The modeling approach is explained. The advantage of using behavioural models is highlighted. The resulting simulations are consistent with transistor level simulation results, but several orders of magnitude faster. The resulting design achieves a performance that is comparable with designs using current techniques, but with significantly reduced area.
Starting Page	5174
Ending Page	5177
File Size	213035
Page Count	4
File Format	PDF
ISBN	0780388348
DOI	10.1109/ISCAS.2005.1465800
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops Semiconductor device modeling Circuit topology Circuit testing Analog integrated circuits CMOS analog integrated circuits CMOS integrated circuits CMOS digital integrated circuits CMOS process Capacitors
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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