NDLI: Minimal activity mixed-signal VLSI architecture for real-time linear transforms in video

Content Provider	IEEE Xplore Digital Library
Author	Karakiewicz, R. Genov, R.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada (Karakiewicz, R.; Genov, R.)
Abstract	The mixed-signal processor performs digital vector-matrix multiplication using internally analog fine-grain parallel computing. The three-transistor CID/DRAM unit cell combines single-bit dynamic storage, binary multiplication, and zero-latency analog accumulation. Matrix coefficients are stored in a bit-parallel form. Delta-sigma analog-to-digital conversion of the analog array outputs is combined with oversampled unary coding of the digital inputs. Sorting of unary inputs results in at most a single input line transition for arbitrary multi-bit inputs. This amounts to a linear gain in energy efficiency of the computational array in the number of bits of the input vector. The 256 /spl times/ 128 CID/DRAM processor with integrated 128 delta-sigma ADC measures 3 mm /spl times/ 3 mm in 0.5 /spl mu/m CMOS and delivers 6.5 GMACS dissipating 5.9 mW of power. CID/DRAM array dynamic power dissipation is reduced by a factor of four through sorting 8-bit inputs.
Starting Page	4433
Ending Page	4436
File Size	231987
Page Count	4
File Format	PDF
ISBN	0780388348
DOI	10.1109/ISCAS.2005.1465615
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Random access memory Sorting Computer architecture Parallel processing Analog-digital conversion Gain Energy efficiency Vectors Power measurement
Content Type	Text
Resource Type	Article

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