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2005 IEEE International Symposium on Circuits and Systems
A 32/spl times/24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure
A start-up calibration method for generic current-steering D/A converters with optimal area solution
Two dimensional nonuniform perfect reconstruction filter bank with irrational down-sampling matrices
A novel substrate-triggered ESD protection structure for a bus switch IC with on-chip substrate-pump
A 16,000-gate-count optically reconfigurable gate array in a standard 0.35 /spl mu/m CMOS technology
A near-infrared heart rate sensor IC with very low cutoff frequency using current steering technique
Robust super-exponential methods for blind equalization of SISO systems with additive Gaussian noise
Low redundancy layered multiple description scalable coding using the subband extension of H.264/AVC
A spiking silicon central pattern generator with floating gate synapses [robot control applications]
Properties and relations of ternary linearly independent transforms [multivalued logic applications]
A 5 GHz sub-harmonic direct down-conversion mixer for dual-band system in 0.35 /spl mu/m SiGe BiCMOS
Thunderstorm tracking system using neural networks and measured electric fields from few field mills
New architecture of realizing seamless connectivity and cooperative control for home network systems
A background correction technique for timing errors in time-interleaved analog-to-digital converters
A 2 V 0.25 /spl mu/m CMOS 250 MHz fully-differential seventh-order equiripple linear phase LF filter
