NDLI: Minimizing power with flexible voltage islands

Please wait, while we are loading the content...

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

2012 IEEE International Conference on Circuits and Systems (ICCAS)

2012 IEEE International Symposium on Circuits and Systems

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

2009 IEEE International Symposium on Circuits and Systems

2008 IEEE International Symposium on Circuits and Systems

2007 IEEE International Symposium on Circuits and Systems

2006 IEEE International Symposium on Circuits and Systems

2005 IEEE International Symposium on Circuits and Systems

IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE Cat. No. 05CH37618)

Asymmetric halo CMOSFET to reduce static power dissipation with improved performance

Limits to performance spread tuning using adaptive voltage and body biasing

Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power

Device technology for body biasing scheme

Optimum threshold-voltage tuning for low-power, high-performance microprocessor

Minimizing power with flexible voltage islands

Robust VLSI architecture for system-on-chip design and its implementation in Viterbi decoder

A systematic framework for high throughput MAP decoder VLSI architectures

System on chip FPGA design of an FM demodulator using a Kalman band-pass sigma-delta architecture

High level hardware/software communication estimation in shared memory architecture

A novel low-power reconfigurable FFT processor

Concentrator access networks for programmable logic cores on SoCs

A collision-based model for multi user interference in impulse radio UWB networks

On the acquisition time for serial and parallel code search in UWB impulse radio

Ultra-low power UWB for real time biomedical wireless sensing

Digitizing of UWB signals based on frequency channelization

Quasi-cyclic low-density parity-check coded multi-band-OFDM UWB systems

A novel covalent redundant binary Booth encoder

A 32/spl times/24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure

A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability

A framework for the design of error-aware power-efficient fixed-width Booth multipliers

A novel multiplexer based truncated array multiplier

A combined two's complement and floating-point comparator

A global interconnect optimization algorithm under accurate delay model using solution space smoothing

An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models

Zero skew clock routing with tree topology construction using simulated annealing method

A sparsified vector potential equivalent circuit model for massively coupled interconnects

An efficient algorithm for simultaneous wire permutation, inversion, and spacing

Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires

An electron mobility independent pulse skipping regulator for a programmable CMOS charge pump

High-efficiency control structure for CMOS flash memory charge pumps

Integration of high voltage charge-pumps in a submicron standard CMOS process for programming analog floating-gate circuits

Optimum quiescent point of integrated power CMOS transistor for wireless portable applications

Design technique of an on-chip, high-voltage charge pump in SOI

A monolithic isolation amplifier in silicon-on-insulator CMOS

A specific integrated controller for nanomicroscopy and cellular manipulation

A distributed neural signal sensor system

Automatic detection of region of interest and center point of left ventricle using watershed segmentation

Assessment of driver's driving performance and alertness using EEG-based fuzzy neural networks

Classification of driver's cognitive responses from EEG analysis

Partitioning graphs of supply and demand

Advances in QoS path(s) selection problem

On generating elementary T-invariants of Petri nets by linear programming

Hierarchical extraction of a spanning planar subgraph maintaining clockwise directedness of cycles

Scheduling problems for a class of parallel distributed systems

On the three-dimensional channel routing

An energy-efficient charge recycling approach for a SAR converter with capacitive DAC

Novel successive-approximation algorithms

A 1V supply successive approximation ADC with rail-to-rail input voltage range

A new switch compensation technique for inverted R-2R ladder DACs

A new offset cancellation technique for folding ADC

Characterization and noise analysis of a 12-bit current steering digital-to-analog converter

High linear digitally programmable gain amplifier

Impact of bias schemes on Doherty power amplifiers

High current CMOS operational amplifier

Design of a 0.8 Volt fully differential CMOS OTA using the bulk-driven technique

Design and analysis of a micropower low-voltage bang-bang control class D amplifier

Op amp tuning for high accuracy deep sub-micron CMOS analog circuits [voltage regulator example]

Formal synthesis of circuits using linear matrix inequalities

Multiple resonance networks with incomplete energy transfer and operating with zero-state response

The separability, reducibility and controllability of RLCM networks over F(z)

Symbolic passive-RC circuit synthesis by admittance matrix expansion

Symbolic active-RC circuit synthesis by admittance matrix expansion

Generation of equivalent circuits by FTFN relocation

An active noise control system based on simultaneous equations method without auxiliary filters

A filtered-X RLS based narrowband active noise control system in the presence of frequency mismatch

A method for online secondary path modeling in active noise control systems

Active noise cancellation headset

A new noise reduction system based on ALE and noise reconstruction filter

Adaptive noise equalizer with equal-loudness compensation

Chaotic and periodic spreading dynamics in discrete small-world networks

Pinning control of scale-free complex networks

On-off intermittency in small-world networks of chaotic maps

Agreement and consensus problems in groups of autonomous agents with linear dynamics

3D dynamical networks to emulate complex neural phenomena

Synchronization: a fundamental phenomenon in complex dynamical networks

Linear transform based motion compensated prediction for luminance intensity changes

A feature-based approach to fast H.264 intra/inter mode decision

An improved rate control algorithm for H.264

The technique of pre-scaled integer transform

An improved error concealment algorithm for intra-frames in H.264/AVC

Quantization offsets for video coding

Iterative tri-stage decoding for turbo codes in partial response channels

Analog slice turbo decoding

A memory-based architecture for FPGA implementations of low-density parity-check convolutional decoders

Low complexity parallel Chien search architecture for RS decoder

Area and power efficient trellis computational blocks in 0.13/spl mu/m CMOS

S-code: new distance-3 MDS array codes

Design of low complexity high-speed pulse-shaping IIR filters for mobile communication receivers

Wideband 70dB CMOS digital variable gain amplifier design for DVB-T receiver's AGC

Multi-user receiver using conjugate gradient method for wideband CDMA

An ultra wideband low complexity circuit transceiver architecture for sensor networks

A 15 mW 69 dB 2 Gsamples/s CMOS analog front-end for low-band UWB applications

Design of a fully integrated array of high-voltage digital-to-analog converters

A novel methodology for the design of LC tank VCO with low phase noise

A novel low-power input-independent MOS AC/DC charge pump

Large tuning band range of high frequency filter for wireless applications

Behavioral analysis and dimensioning of UMTS transmitters baseband blocks

A frequency up-conversion and two-step channel selection embedded CMOS D/A interface

A novel DC-offset cancelling circuit for DCR

A digitally programmable on-chip RC-oscillator in 0.25 /spl mu/m CMOS logic process

A novel microstrip bandpass filter design using asymmetric parallel coupled-line

Pipelining Tomlinson-Harashima precoders

Low cost efficient architecture for H.264 motion estimation

Novel electrostatic discharge protection structure for a monolithic gas sensor systems-on-a-chip

On-board fault-tolerant SAR processor for spaceborne imaging radar systems

Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams

Design space exploration on heterogeneous network-on-chip

A simple and cost effective video encoder with memory-reducing CAVLC

An integrated current flattening module for embedded cryptosystems

A pseudo-differential CMOS receiver insensitive to input common mode level

Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits

High-speed CMOS-to-ECL pad driver in 0.18 /spl mu/m CMOS

A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter

Case study of interconnect analysis for standing wave oscillator design

Asynchronous pulse logic cell for threshold logic and Boolean networks

Cascode buffer for monolithic voltage conversion operating at high input supply voltages

Characteristics and programming of floating-gate pFET switches in an FPAA crossbar network

A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard

Quaternary arithmetic helix transforms based on Kronecker product

Generalized fastest linearly independent arithmetic transforms

Fixed sign Walsh transform and its iterative hardware architecture

Generation of linearly independent transforms over GF(4)

A high performance architecture of EBCOT encoder in JPEG 2000

Comparison of the horizontal and the vertical common subexpression elimination methods for realizing digital filters

Complex-coefficient variable filter design using successive vector-array-decomposition

Non-iterative WLS design of allpass variable fractional-delay digital filters

Discrete optimization for error feedback network using lower bound estimation

Design of a square-root-raised-cosine FIR filter by a recursive method

Pole deviation analysis for digital systems based on second order perturbation theory [digital filter example]

A hybrid GA for the design of multiplication-free frequency response masking filters [FIR digital filters]

Pulse shaping with bireciprocal wave digital lattice filters

Design and FPGA implementation of a structure of evolutionary digital filters for hardware implementation

A novel 2D filter design methodology

Synthesis of reconfigurable multiplier blocks: part I - fundamentals

Synthesis of reconfigurable multiplier blocks: part - II algorithm

A hardware-efficient FIR architecture with input-data and tap folding

Residue number system implementations of complex heterodyne tunable filters

Low complexity decimation filter for multi-standard digital receivers

Stability of a shift-variant 2-D state-space digital filter

A time-to-digital-converter-based CMOS smart temperature sensor

High-speed sensing system for depth estimation based on depth-from-focus by using smart imager

A CMOS imager for light blobs detection and processing

Design of electro-optical demodulating pixel in CMOS technology

Digital measurement of human proximity to electrical power circuit by a novel amplitude-shift-keying radio-frequency receiver

Low-power global/rolling shutter image sensors in silicon on sapphire technology

Low power current mode ADC for CMOS sensor IC

A wide dynamic range CMOS active pixel sensor with frame difference

Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses

Low power repeaters driving RLC interconnects with delay and bandwidth constraints

Low-leakage repeaters for NoC interconnects

Power-aware global signaling strategies

Designing optimized pipelined global interconnects: algorithms and methodology impact

Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment

Battery-aware dynamic voltage scaling in multiprocessor embedded system

Noise coupling in multi-voltage power distribution systems with decoupling capacitors

A 16-bit low-power microcontroller with monolithic MEMS-LC clocking

A fast chip-scale power estimation method for large and complex LSIs based on hierarchical analysis

An LSI system with locked in temperature insensitive state achieved by using body bias technique

An energy-efficient circuit technique for single event transient noise-tolerance

Decentralized energy-conserving and coverage-preserving protocols for wireless sensor networks

Event-based imaging with active illumination in sensor networks

On the construction of efficient data gathering tree in wireless sensor networks

A RF map-based localization algorithm for indoor environments

A new formulation of fast diminished-one multioperand modulo 2/sup n/+1 adder

Non-interleaving architecture for hardware implementation of modular multiplication

A new design method to modulo 2/sup n/-1 squaring

Constant addition utilizing flagged prefix structures

Efficient VLSI implementation of N/N integer division

A novel design of leading zero anticipation circuit with parallel error detection

High-level synthesis under I/O timing and memory constraints

A low power scheduling method using dual V/sub dd/ and dual V/sub th/

A synthesis scheme for simultaneous scheduling, binding, partitioning and placement with resources operating at multiple voltages

A heuristic approach for multiple restricted multiplication

Lower-bound estimation for multi-bitwidth scheduling

Statistical schedule length analysis in asynchronous datapath synthesis

Comparison of two class E amplifiers for EER transmitter

Steady-state behavior of class E amplifier outside designed conditions

Voltage-clamped class E amplifier with transmission-line transformer

Optimum design of very low distortion class E power amplifiers

Resonant DC/DC converter with class E oscillator

Planar inductors with interleaved conductors for integrated power applications

A novel correlated double sampling poly-Si circuit for readout systems in large area X-ray sensors

On-chip active power rectifiers for biomedical applications

A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications

A 0.9-V 67-/spl mu/W analog front-end using adaptive-SNR technique for digital hearing aid

A BiCMOS ENG amplifier with high SIR output

10-channel very low noise ENG amplifier system using CMOS technology

Minimum augmentation to bi-connect specified vertices of a graph with upper bounds on vertex-degree

A modeling method of a rule based control system with hierarchical Petri net

Minimal time reachability problem of some subclasses of timed Petri nets

The node voltage equations and structural conditions of observability for RLC networks over F(z)

Graph-theoretic approach to the design of four-switch DC-DC converters

Simplified algorithm to determine break point realys & relay coordination based on network topology [for realys read relays]

A low-distortion 1.2 V DAC+filter for transmitters in wireless applications

Adjustable gamma correction circuit for TFT LCD

A segmented thermometer coded DAC with deterministic dynamic element matching for high resolution ADC test

A start-up calibration method for generic current-steering D/A converters with optimal area solution

Pipeline ADC linearity testing with dramatically reduced data capture time

On-chip built-in self-test of video-rate ADCs using Gaussian noise

A 0.18 /spl mu/m CMOS low-noise elliptic low-pass continuous-time filter

Low sensitivity single-ended-input OTA and grounded capacitor elliptic filter structure with the minimum components

Low-sensitivity active-RC filters using impedance tapering of symmetrical bridged-T and twin-T networks

A widely tunable Gm-C filter using tail current offset in two differential pairs

A comparison approach of lowpass type wave active filter using unified circuit block

Single amplifier bi-quadratic filter topologies in transimpedance configuration

Quantum circuit design of discrete Hartley transform using recursive decomposition formula

Quantum circuit design of 8/spl times/8 discrete cosine transform using its fast computation flow graph

Hermite-Gaussian-like eigenvectors of the DFT matrix generated by the eigenanalysis of an almost tridiagonal matrix

An approach for computing the radix-2/4 DIT FHT and FFT algorithms using a unified structure

Design of wavelet filters based on digital complex allpass filters

Block time-recursive discrete Gabor transform implemented by unified parallel lattice structures

Rate determination based on perceptual loudness

A mixed analog-digital hybrid for speech enhancement purposes

Adaptive beamformer for hands-free communication system in noisy environments

Audio classification and scene recognition and for hearing aids

A versatile speech enhancement system based on perceptual wavelet denoising

Improved voice activity detection via contextual information and noise suppression

Approximations for bit error probabilities in SSMA communication systems using spreading sequences of Markov chains

Optimal spreading in multi-user non-coherent binary chaos-shift-keying communication systems

Cryptanalysis of a multistage encryption system

Design of code-matched receiver for DS/CDMA communications

Coded modulation based on higher dimensional chaotic maps

Long period pseudo random bit generators derived from a discretized chaotic map

Frame size selection in video downsizing transcoding application

A novel algorithm for reducing computational complexity of MC-DCT in frequency-domain video transcoders

Efficient video transcoding between H.263 and H.264/AVC standards

Low complexity H.263 to H.264 video transcoding using motion vector decomposition

Consideration of transcoding using updatable scalability for selective quality video content delivery method

Flexible resizing algorithms for video transcoding

A low-power, 20-Gb/s continuous-time adaptive passive equalizer

Adaptive decision-feedback equalization for band-limited high-speed serial links

Joint carrier recovery and adaptive equalization for high-order QAM

Hardware realization of fuzzy adaptive filters for non linear channel equalization

Jitter equalization for binary baseband communication

Predictive equalizer design for DVB-T system

Progressive coding of 3D dynamic mesh sequences using spatiotemporal decomposition

Progressive lossless 3D mesh encoder with octree-based space partitioning

Fast region-of-interest transcoding for JPEG 2000 images

Construction of regular 3D point clouds using octree partitioning and resampling

Slice group based multiple description video coding with three motion compensation loops

Improving classification of video shots using information-theoretic co-clustering

The upper bound of the second-order modes of linear state-space systems [digital filter example]

A novel property of the second-order modes of discrete-time systems under variable transformation

Special singularity integrals encountered in electric circuits [RLC circuit examples]

Identification of electric circuits: problems and methods of solution accuracy enhancement

On the effect of time delays in negative feedback amplifiers

Jittered uniform sampling - examples

Testability evaluation for analog linear circuits via transfer function analysis

Synthesis of MITE log-domain filters with unique operating points

Low voltage high current gain CMOS digitally controlled fully differential CCII [variable gain amplifier application example]

A new NMOS four-quadrant analog multiplier

Class-AB rail-to-rail CMOS analog buffer

IC design of an analog tunable crossover network

A /spl plusmn/ 1.5 V high frequency four quadrant current multiplier

CMOS analog current-mode multiplier based on the advanced compact MOSFET model

On-chip temperature sensor with high tolerance for process and temperature variation

A current mode Palmo cell for programmable analogue signal processing

A memory-reduced log-MAP kernel for turbo decoder

An ultra high-speed Reed-Solomon decoder

A new low-power turbo decoder using HDA-DHDD stopping iteration

Communication subsystem synthesis and analysis tool using bus architecture generation and stochastic arbitration policies

Efficient implementation of trace-back unit in a reconfigurable Viterbi decoder fabric

A new reconfigurable modem architecture for 3G multi-standard wireless communication systems

A 12.5 Gbps CMOS input sampler for serial link receiver front end

Low-power current mode logic for improved DPA-resistance in embedded systems

A new level-up shifter for high speed and wide range interface in ultra deep sub-micron

A novel CMOS logic style with data independent power consumption

A phase-detect synchronous mirror delay for clock skew-compensation circuits

A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications

A linear model for high-level delay estimation in VDSM on-chip interconnects

A closed-form delay formula for on-chip RLC interconnects in current-mode signaling

Two dimensional nonuniform perfect reconstruction filter bank with irrational down-sampling matrices

Multidimensional filter banks design by direct optimization

On the theory and design of a class of PR causal-stable IIR non-uniform recombination cosine modulated filter banks

Design of two-channels FIR filterbanks with rational sampling factors using the FRM technique

Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter

Optimized transmultiplexers for multirate systems

A class of directional filter banks [image processing applications]

Filter bank design for an adaptive subband structure with critical sampling using a new adaptation scheme

Architectural design of fractal image coder based on kick-out condition

Dictionary-based program compression on transport triggered architectures

Techniques for efficient DCT/IDCT implementation on generic GPU

High-performance systolic arrays for band matrix multiplication

Block-level parallel processing for scaling evenly divisible frames

Parallel FFT computation with a CDMA-based network-on-chip

Hardware accelerator design for video segmentation with multi-modal background modelling

Multiplier-free structures for exact generation of natural powers of integers

A 0.18-/spl mu/m CMOS 1-Gb/s serial link transceiver by using PWM and PAM techniques

3.125 Gb/s power efficient line driver with 2-level pre-emphasis and 2 kV HBM ESD protection

A 0.18 /spl mu/m CMOS transceiver design for high-speed backplane data communications

A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs

An electrically adjustable distributed pulse shaping filter for 40 Gbit/s optical links

Dual-loop control of laser drivers for 3.125GHz optical transceivers

A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit

An high speed integrated equalizer for dispersion compensation in 10Gb/s fiber networks

ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure

A novel substrate-triggered ESD protection structure for a bus switch IC with on-chip substrate-pump

ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies

A new pre-driver design for improving the ESD performance of the high voltage tolerant I/O

On-chip ESD protection for RF I/Os: devices, circuits and models

A methodology for partitioning DSP applications in hybrid reconfigurable systems

A new approach based on LFF for optimization of dynamic hardware reconfigurations

A 16,000-gate-count optically reconfigurable gate array in a standard 0.35 /spl mu/m CMOS technology

Pipelining technique for energy-aware datapaths

A low power FPGA routing architecture

Efficient high radix modular multiplication for high-speed computing in re-configurable hardware [cryptographic applications]

Motion information and coding mode reuse for MPEG-2 to H.264 transcoding

Efficient MPEG-2 to H.264/AVC intra transcoding in transform-domain

Efficient rate control for MPEG-2 to H.264/AVC transcoding

R-D optimized quantization of H.264 SP-frames for bitstream switching under storage constraints

Fast mode decision and motion estimation for H.264 with a focus on MPEG-2/H.264 transcoding

Optimizing user expectations for video semantic filtering and abstraction

Analytical crosstalk noise and its induced-delay estimation for distributed RLC interconnects under ramp excitation

An all-digital pulsewidth control loop

Design of a new sense amplifier flip-flop with improved power-delay-product

A 1.2 V sense amplifier for high-performance embeddable NOR flash memories

SET and RESET pulse characterization in BJT-selected phase-change memories

Decision feedback equalization for high-speed backplane data communications

Interconnect model reductions by using the AORA algorithm with considering the adjoint network

Parameter domain pruning for improving convergence of synthesis algorithms

Enriching an analog platform for analog-to-digital converter design

Parametric model order reduction technique for design optimization

Design automation of single-ended LNAs using symbolic analysis

Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization

Efficiency optimization in linear-assisted switching power converters for envelope tracking in RF power amplifiers

Hybrid trigonometric differential evolution for optimizing harmonic distribution

Hybrid switched-capacitor-Cuk/Zeta/Sepic converters in step-up mode

High efficiency wide bandwidth power supplies for GSM and EDGE RF power amplifiers

Boost-buck inverter variable structure control for grid-connected photovoltaic systems

Thinned-out controlled class D inverter with delta-sigma modulated 1-bit driving pulses

Modeling external feedback path of an ITE digital hearing instrument for acoustic feedback cancellation

A dual-mode wavelet based R-wave detector using single-V/sub t/ for leakage reduction [cardiac pacemaker applications]

An efficient ECG data compression technique based on predefined signature and envelope vector banks

The CRLB for bilinear systems and its biomedical applications

Scalable architecture for streaming neural information from implantable multichannel neuroprosthetic devices

A novel CMOS lab-on-a-chip for biomedical applications

Probabilistic congestion prediction in hierarchical quad-grid model

Small congestion embedding of separable graphs into grids of the same size

On VLSI decompositions for d-ary de Bruijn graphs (extended abstract)

Approximation algorithms for the rectilinear Steiner tree problem with obstacles

Wiring area optimization in floorplan-aware hierarchical power grids

Timing-driven Steiner tree construction based on feasible assignment of hidden Steiner points

A robust background calibration technique for switched-capacitor pipelined ADCs

A digital self-calibration algorithm for ADCs based on histogram test using low-linearity input signals

A linear-approximation technique for digitally-calibrated pipelined A/D converters

Design of a 2-GS/s 8-b self-calibrating ADC in 0.18 /spl mu/m CMOS technology

Background calibration of interleaved analog to digital converters for high-speed communications using interleaved timing recovery techniques

Spectral shaping of timing mismatches in time-interleaved analog-to-digital converters

Programmable switched-current floating-gate cells

Time-interleaved switched-capacitor filter for reconfigurable triple-band delta-sigma converter

A novel current-conveyor-based switched-capacitor integrator

A new multiply-by-two gain-stage with enhanced immunity to capacitor-mismatch

Inverter-based switched current circuit for very low-voltage and low-power applications

A high speed, high resolution, low voltage current mode sample and hold

An improved algorithm for maximum-likelihood based approach for a multitarget tracking problem

Optimal periodic sampling sequences for nearly-alias-free digital signal processing

Normalized confidence factors for robust direction of arrival estimation

An efficient method for estimation of autoregressive signals in noise

Symbol-rate estimation based on filter bank

Pilot-aided DOA estimation for CDMA communication systems

New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination

Implementation of low-complexity FIR filters using serial arithmetic

A low power decimation filter architecture for high-speed single-bit sigma-delta modulation

A high performance distributed-parallel-processor architecture for 3D IIR digital filters

A VLSI architecture for a high-speed computation of the 1D discrete wavelet transform

Memory access overhead reduction for a digital color copier implementation using a VLIW digital signal processor

Horseshoes, homoclinic connections and global chaos in current-mode controlled DC/DC converters

N-scroll chaotic attractors from a general jerk circuit

Solvable 2-dimensional rational chaotic map defined by Jacobian elliptic functions

Back propagation learning of neural networks with chaotically-selected affordable neurons

On two-parameter non-smooth bifurcations in power converters

Experimental performance evaluation of a low-EMI chaos-based current-programmed DC/DC boost converter

An adaptive fast full search motion estimation algorithm for H.264

Transform-domain intra prediction for H.264

An improved frame and macroblock layer bit allocation scheme for H.264 rate control

Fast multi-frame motion estimation for H.264 and its applications to complexity-aware streaming

Fast three step intra prediction algorithm for 4/spl times/4 blocks in H.264

Fast block motion estimation with early acceptance technique in H.264/JVT

Development of a microwave receiving and transmission system using an optical modulator

A comparison of equalizers for compensating polarization-mode dispersion in 40-Gb/s optical systems

A 0.18-/spl mu/m 10-GHz CMOS ring oscillator for optical transceivers

Four-channel CMOS photoreceiver array for parallel optical interconnects

A switched delay line based optical switch architecture with a bypass line

A 400Mbps CMOS spatially-modulated photoreceiver for optical storage

MIRROR: an interactive content based image retrieval system

Scheduling design for distributed video-on-demand servers

Program segmentation for TV videos

Content-based scalable sports video retrieval system

A novel BP-based image retrieval system

A 110 dB CMRR/PSRR/gain CMOS operational amplifier

Hybrid cascode compensation for two-stage CMOS operational amplifiers

High-performance CMOS pseudo-differential amplifier

High-performance CMOS current feedback operational amplifier

A design of controllable gain class B push-pull current amplifier

A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits

A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits

Current-mode universal biquad circuit using MO-OTAs and DO-CCII

A low-power method adding continuous variable gain to amplifiers

Design consideration for lowering sensitivity to out of band interference of negative feedback amplifiers

A 2.4 GHz 82 dB/spl Omega/ fully differential CMOS transimpedance amplifier for optical receiver based on wide-swing cascode topology

Cascaded double-stage configuration for high-performance broadband amplification in CMOS

Influence of frequency compensation on the linearity of negative feedback amplifiers

A 3 Gb/s 80 dB CMOS differential transimpedance amplifier for optical communication systems

Power dependence of feedback amplifiers on opamp architecture

Digitally controlled fully differential current conveyor: CMOS realization and applications

A sub-word-parallel Galois field multiply-accumulate unit for digital signal processors

A configurable dual moduli multi-operand modulo adder

An MCML four-bit ripple-carry adder design in 1 GHz range

Low power parallel multiplier with column bypassing

Design of power-aware multiplier with graceful quality-power trade-offs

Equalizing data-path for processing speed determination in block level pipelining

Dual sense amplified bit lines (DSABL) architecture for low-power SRAM design

A low-leakage twin-precision multiplier using reconfigurable power gating

An energy-efficient skew compensation technique for high-speed skew-sensitive signaling

Area, power, and pin efficient bus transceiver using multi-bit-differential signaling

Enhancing the efficiency of cluster voltage scaling technique for low-power application

A low-power high-SFDR CMOS direct digital frequency synthesizer

Domino logic with an efficient variable threshold voltage keeper

A low dynamic power and low leakage power CMOS square-root circuit

A robust adaptive cross microphone array

A combined TDA/FDA adaptive schema for stereophonic acoustic echo cancellation

Image encryption using progressive cellular automata substitution and SCAN

Study of a least-squares type method for noisy FIR filtering

Optimal user weighting fusion in DWT domain on-line signature verification

A hardware generator for multi-point distributed random variables

Direct-digital synthesis using delta-sigma modulated signals

Performance of a type-based digital predistorter for solid-state power amplifier linearization

Diversity gain's influence on MIMO's detection

Multiuser scheduling for downlink in multi-antenna wireless systems

Robust adaptive channel estimation of OFDM systems in time-varying narrowband interference

Joint frequency offset estimation and multiuser detection using genetic algorithm in MC-CDMA

Reduced-rank antenna selection for MIMO DS-CDMA channels

Performance of the pulse pair method with an optimal lag value for frequency estimation in fading channels

Integrated mixed-signal optoelectronic system-on-a-chip sensor

A 60 ns 500/spl times/12 0.35 /spl mu/m CMOS low-power scanning read-out IC for cryogenic infra-red sensors

Instrumentation of YSZ oxygen sensor calibration in liquid lead-bismuth eutectic

An automatic acoustic bathroom monitoring system

A PWM DPS with pixel-level reconfigurable 4/8-bit counter/SRAM

Sensor array for multiple emission gas measurements

Pulse-based interface circuits for SPR sensing systems [analyte concentration measurement]

Network-on-chip-centric approach to interleaving in high throughput channel decoders

Power analysis of link level and end-to-end data protection in networks on chip

Effect of traffic localization on energy dissipation in NoC-based interconnect

A methodology for design, modeling, and analysis of networks-on-chip

Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip

VLSI architecture based on packet data transfer scheme and its application

Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC

A novel VLSI architecture for VBSME in MPEG-4 AVC/H.264

Architecture of global motion compensation for MPEG-4 advanced simple profile

Combined 2-D transform and quantization architectures for H.264 video coders

Combined frame memory architecture for motion compensation in video decoding

An H.264/AVC decoder with 4/spl times/4-block level pipeline

Multiplication by two integers using the minimum number of adders

Signed power-of-two allocation scheme for the design of lattice orthogonal filter banks

I/sup 2/CRA: contention resolution algorithm for intra- and inter-coefficient common subexpression elimination

Design and implementation of multiplierless adjustable fractional-delay all-pass filters

Design of FIR digital filters with discrete coefficients via convex relaxation

Further complexity reduction of parallel FIR filters

Glitch-free discretely programmable clock generation on chip

A three-level toggle-avoid bus signaling scheme

A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch

A distributed FIFO scheme for on chip communication

A multifunctional high-voltage driver chip for low-power mobile display systems

Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications

Performance constrained floorplanning based on partial clustering [IC layout]

Wire-driven microarchitectural design space exploration

Integrated routing resource assignment for RLC crosstalk minimization

Placement for the reconfigurable datapath architecture

Simple yet effective algorithms for block and I/O buffer placement in flip-chip design

Fixed-outline floorplanning with constraints through instance augmentation

High light-load efficiency charge pumps

Efficiency comparison between doubler and Dickson charge pumps

Charge redistribution loss consideration in optimal charge pump design

A 5V charge pump in a standard 1.8-V 0.18-/spl mu/m CMOS process

Heap charge pump optimisation by a tapered architecture

Gate control strategies for high efficiency charge pumps

Quantization errors in committee machine for gas sensor applications

A 100/spl times/100 pixels orientation-selective multi-chip vision system

A real-time spike-domain sensory information processing system [image processing applications]

Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters

Rich spike-synchronization phenomena of pulse-coupled bifurcating neurons

Novel /spl mu/-power log-domain integrators

A low voltage CMOS multiplier for high frequency equalization

A low current consumption CMOS latched comparator for body-implanted chip

On the analog generation of pink noise from white noise

Integrating lumped networks into full wave TLM/FDTD methods using passive discrete circuit models

Field programmable Gm-C array for wide frequency range bandpass filter applications

Accuracy limitations of pipelined ADCs

A new ratio-independent A/D conversion technique for high-resolution pipeline A/D converters

Design and optimization of multi-bit front-end stage and scaled back-end stages of pipelined ADCs

kT/C constrained optimization of power in pipeline ADCs

A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques

Full calibration digital techniques for pipeline ADCs

A low-power, programmable bandpass filter section for higher-order filter-bank applications

Low-voltage programmable g/sub m/-C filter for hearing aids using dynamic gate biasing

A compact nA/V CMOS triode-transconductor and its application to very-low frequency filters

Wave log-domain filters

Complex wave filters and wave group-delay equalisers in log-domain

1 V compact class-AB CMOS log filters

Symmetry-based analytically closed-form design of variable fractional-delay FIR digital filters

A decomposition technique for cascaded IIR-like filter blocks generating linear-phase FIR filters

Synthesis of narrowband linear-phase FIR filters with a piecewise-polynomial impulse response

Interpolation factor analysis for jointly optimized frequency-response masking filters

A novel low-complexity method for parallel multiplierless implementation of digital FIR filters

Design of complex FIR filters using the frequency-response masking approach

A new minimax design for 2D FIR filters with low group delay

A low-complexity scanned-array 3D IIR frequency-planar filter

A perfect reconstruction filter bank with irrational down-sampling factors

Fractional polynomials and nD systems

A constructive procedure for multidimensional realization and LFR uncertainty modelling

Demosaicing with improved edge direction detection

Approximate optimal demodulation for multi-user binary coherent chaos-shift-keying communication systems

A novel code acquisition algorithm and its application to Markov spreading codes

Stroboscopic model and bifurcations in TCP/RED

An analog-to-digital converter with dynamic window for optimal rational number approximation

Wavelet-based estimation of long-range dependence in MPEG video traces

Nonlinear output feedback control of TCP/AQM networks

Reduced latency arithmetic decoder for JPEG2000 block decoding

Matching pursuits using slant patterns and its dictionary design [video coding applications]

Image compression with interpolation in wavelet-transform domain

An image compression scheme based on parametric Haar-like transform

Lifting-based multi-view image coding

High quality Motion JPEG2000 coding scheme based on the human visual system

A full-range all-pass variable phase shifter for multiple antenna receivers

Design considerations for a 10 GHz CMOS transmit-receive switch

A gain/phase mismatch calibration procedure for RF I/Q downconverters

8 GHz tunable CMOS quadrature generator using differential active inductors

A 5.25 GHz CMOS even harmonic mixer with an enhancing inductance

A new CMOS wideband RF front-end for multistandard low-IF wireless receivers

An integrated rate control scheme for TCP-friendly MPEG-4 video transmission

Improved and fast algorithms for intra 4/spl times/4 mode decision in H.264/AVC

Tightly-coupled MPEG-4 video encoder framework on asymmetric dual-core platforms

Hardware-efficient computing architecture for motion compensation interpolation in H.264 video coding

A memory-efficient deblocking filter for H.264/AVC video coding

Variable frame rate transcoding considering motion information [video transcoding]

Programming analog computational memory elements to 0.2% accuracy over 3.5 decades using a predictive method

Ramp voltage supply using adiabatic charging principle

A 0.8 V, 360 nW Gm-C biquad based on FGMOS transistors [biquadratic filter]

A 0.9 V offset compensated FGMOS comparator

Biasing techniques for subthreshold MOS resistive grids

Programmable floating-gate CMOS resistors

Indirect programming of floating-gate transistors

A fully differential line driver with on-chip calibrated source termination for gigabit and fast Ethernet in a standard 0.13/spl mu/ CMOS process

Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface

A CMOS front-end architecture for hard-disk drive read-channel equalizer

Soft fault test and diagnosis for analog circuits

A clock recovery circuit using half-rate 4/spl times/-oversampling PD

Built-in current sensor with reduced voltage drop using thin-film transistors

Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization

Digital built-in self-test of CMOS analog iterative decoders

Built-in self-test for automatic analog frequency response measurement

Linear-time algorithm for computing minimum checkpoint sets for simulation-based verification of HDL programs

The chaotic numbers of the bipartite and tripartite graphs

Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation

Efficient computation of dominators in multiple-output circuit graphs

Hardware reduction using a 6-connectivity interconnection network over a 4-connectivity VLSI asynchronous array processor

Maximum weight matching-based algorithms for k-edge-connectivity augmentation of a graph

An AQM routing control for reducing congestion in communication networks

GA-based applications for routing with an upper bound constraint

Analyses of intermodulation effects in fractional-N frequency synthesis

Behavioral modeling and simulation of weakly nonlinear sampled-data systems

Analytical expression of HD3 due to non-linear MOS switch in MOSFET-C sample and hold circuits

Analysis of jitter peaking and jitter accumulation in re-circulating delay-locked loops

Root iterations and the computation of minimum and maximum zeros of polynomials

Phase noise spectra analysis for LC oscillators

A model-based approach for the development of LMS algorithms [adaptive filter applications]

A new approach for non-uniform subband adaptive filtering

Adaptive filtering using constrained subband updates

Performance of two novel fast affine projection adaptation algorithms

Coordinate descent iterations in pseudo affine projection algorithm

Adaptive IIR notch filters: state-space approach

Structured stochastic optimization strategies for problems with ill-conditioned error surfaces

Modified Taylor-series method for source and receiver localization using TDOA measurements with erroneous receiver positions

Generalized n-dimensional k-order systems: computing the transfer function

Hilbert pair of wavelets via the matching design technique [matched filters]

The missing observations theorem and a new proof of Levinson's recursion

On the time-frequency content of Weyl-Heisenberg frames generated from odd and even functions [signal representation applications]

Image compression using texture modeling

Unconstrained functional criteria for canonical correlation analysis

Some properties of generalized 2-D mirror image and anti mirror image polynomials

Simulation of quantum cellular automaton circuits based on genetic simulated annealing algorithm

Why area might reduce power in nanoscale CMOS

Quantum circuits for stabilizer codes

Exact noise analysis of a CMOS BDJ APS

A novel oscillation circuit using a resonant-tunneling diode

Low-power spatial computing using dynamic threshold devices

On the impact of traffic statistics on quality of service for networks on chip

Slack-time aware routing in NoC systems

An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip

Self-calibrating networks-on-chip

A novel approach for network on chip emulation

A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip

VLSI architectures for stereoscopic video disparity matching and object extraction

Parallel algorithm for hardware implementation of inverse halftoning

Real-time image compression based on wavelet vector quantization, algorithm and VLSI architecture

Partial encryption of compressed images employing FPGA

A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering

VLSI architecture design for a fast parallel label assignment in binary image

A novel low-complexity spatio-temporal ultra wide-angle polyphase cone filter bank applied to sub-pixel motion discrimination

Minimization of L/sub 2/-sensitivity for a class of 2D state-space digital filters subject to L/sub 2/-scaling constraints

An efficient multidimensional decimation-in-frequency FHT algorithm based on the radix-2/4 approach

Generalized /spl alpha/-VSH polynomials and stability of /spl delta/-operator based 2D discrete-time systems

High-resolution DOA estimation by algebraic phase unwrapping algorithm

Optimal construction of compactly-supported multidimensional wavelets

Pre-capturing static pulsed flip-flops

A mathematical programming approach to designing MOS current-mode logic circuits

A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration

An efficient pass-transistor-logic synthesizer using multiplexers and inverters only

An approach to the design of PFSCL gates

Programmable floating-gate techniques for CMOS inverters

Transition time bounded low-power clock tree construction

Timing-driven global routing with efficient buffer insertion

Explicit delay metric for interconnect optimization

Uncertainty modeling of gate delay considering multiple input switching

Timing yield estimation using statistical static timing analysis

A non-iterative equivalent waveform model for timing analysis in presence of crosstalk

A theoretical solution for PWM with non-ideal transient response

Efficiency-oriented switching frequency tuning for a buck switching power converter

Fast-scale instability of single-stage power-factor-correction power supplies

Controlling chaos in DC/DC converters using optimal resonant parametric perturbation

Generalized analysis of integrated magnetic component based low voltage interleaved DC-DC buck converter for efficiency improvement

Wavelet-based piecewise approximation of steady-state waveforms for power electronics circuits [power converter examples]

A new architecture for analog sampled-data neural filters

Annealing robust Walsh function networks for modeling with outliers and digital implementation

Self-organizing neural grove: effective multiple classifier system with pruned self-generating neural trees

Self organizing map based channel prediction for OFDMA

Probabilistic computing with future deep sub-micrometer devices: a modelling approach

Electrical and optical on-chip interconnects in scaled microprocessors

A stepwise constant conductance approach for simulating resonant tunneling diodes

Performance comparison of quantum-dot cellular automata adders

QCA-based nano circuits design [adder design example]

On the functional failure and switching time analysis of the MOBILE circuit [monostable-bistable logic element]

Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture

A new technique for automatic error correction in /spl Sigma//spl Delta/ modulators

Increased jitter sensitivity in continuous- and discrete-time /spl Sigma//spl Delta/ modulators due to finite opamp settling speed

On the effects of finite and nonlinear DC-gain of the amplifiers in switched-capacitor /spl Delta//spl Sigma/ modulators

A multi-mode /spl Sigma//spl Delta/ analog-to-digital converter for GSM, UMTS and WLAN

On reducing leakage quantization noise of multistage /spl Sigma//spl Delta/ modulator using nonlinear oscillation

Design of a high-frequency second-order /spl Delta//spl Sigma/ modulator

Novel and robust constant-g/sub m/ technique for rail-to-rail CMOS amplifier input stages

A constant-g/sub m/ rail-to-rail op amp input stage using dynamic current scaling technique

Constant-g/sub m/ techniques for rail-to-rail CMOS amplifier input stages: a comparative study

Feedforward reversed nested Miller compensation techniques for three-stage amplifiers

Well-defined design procedure for a three-stage CMOS OTA

CMOS single-to-differential current amplifier

Efficient digital filter structures with minimum roundoff noise gain

Design of multiplier-free state-space digital filters

Multi-output passive digital filters

Fourth-order structures for multiplierless realizations of bandpass and bandstop digital filters transformed from all-pole lowpass filters

Design of two-dimensional recursive filters by using a novel genetic algorithm

Wordlength determination algorithms for hardware implementation of linear time invariant systems with prescribed output accuracy

Blind I/Q imbalance compensation in OFDM receivers based on adaptive I/Q signal decorrelation

Peak-to-average power-ratio reduction algorithms for OFDM systems via constellation extension

Decision feedback IBI mitigation in OFDM systems

Fine timing synchronization using power delay profile for OFDM systems

A preamble-aided symbol and frequency synchronization scheme for OFDM systems

New approximate QR-LS algorithms for minimum output energy (MOE) receivers in DS-CDMA communication systems

On phase noise in quadrature cross-coupled oscillators

A precise clock phase multiplier

A spread spectrum clock generator for SATA-II

Robust frequency divider based on resonant tunneling devices

Capacitively averaged multi-phase LC oscillators

Chebyshev approximation of baseband Volterra series for wideband RF power amplifiers

A partitioned linear minimum mean square estimator for error concealment [video decoder error concealment]

The dynamics and stability of layered congestion control for multimedia streaming

Fine-grain layered multicast based on hierarchical bandwidth inference congestion control

Macroblock-based algorithm for dual-bitstream MPEG video streaming with VCR functionalities

20 dBm CMOS class AB power amplifier design for low cost 2 GHz-2.45 GHz consumer applications in a 0.13 /spl mu/m technology

Silicon bipolar linear power amplifier for WCDMA mobile applications

A 2.4 GHz CMOS power amplifier using internal frequency doubling

Development of 4-GHz flip-chip VCO module

Phase noise and amplitude issues of a wide-band VCO utilizing a switched tuning resonator

A study of high-frequency regenerative frequency dividers

Image multi-noise removal by wavelet-based Bayesian estimator

A framework of scalable layered access control for multimedia

Error resilient content-based image authentication over wireless channel

A musical-driven video summarization system using content-aware mechanisms

Load-store reordering for low-power multimedia data transfers

S frame design for multiple description video coding

A near-infrared heart rate sensor IC with very low cutoff frequency using current steering technique

Two preamplifiers for non-invasive on-chip recording of neural-signals

Wide frequency range voltage controlled ring oscillators based on transmission gates

Applying multi-level sliced speech signals to bone-conducted communication

RF-link for cortical neuroprosthesis

Power supply topologies for biphasic stimulation in inductively powered implants

New architecture for miniaturized fluorescence analysis

A foveated AER imager chip [address event representation]

Microactuation of suspended MEMS beams

Three-layer symmetrical and asymmetrical associative memories for image applications

Hybrid sensor network and fusion algorithm for sound source localization

An embedded vision system based on an analog VLSI vision sensor [robot vision applications]

An image pre-processing system employing neuromorphic 100 /spl times/ 100 pixel silicon retina [robot vision applications]

An efficient and well-controlled IC system development flow: design approved specification and design guided test plan

A compound anisotropic diffusion for ultrasonic image denoising and edge enhancement

Neural network ultrasonographic diagnosis system of cirrhosis using DWT for preprocessing

System-on-a-chip (SoC) model of a micropump

A 1.8V low-jitter CMOS ring oscillator with supply regulation

Effective capacitance for gate delay with RC loads

A frequency synthesizer using two different delay feedbacks

Moore test using Gray code

A low spur fractional-N frequency synthesizer architecture

A 1-V 2.4-GHz low-power fractional-N frequency synthesizer with sigma-delta modulator controller

A novel switched-current phase locked loop

Rank identification for an analog ranked order filter

A unified procedure for locating the stabilizable regions of two-dimensional switched systems

Low-frequency bifurcation behaviors of PFC converter

Algebraic representation of error bounds for describing function using Groebner base [nonlinear circuit analysis example]

Investigating stability and bifurcations of a boost PFC circuit under peak current mode control

Learning and recalling of phase pattern in coupled BVP oscillators

Realizing higher-order nonlinear Wiener adaptive systems [Wiener filter example]

Speaker direction tracking using microphones located at the vertices of equilateral-triangle

SoC platform based design of MPEG-2/4 AAC audio decoder

Linear prediction using homomorphic deconvolution in the autocorrelation domain

Multiband room effect simulator for 5.1-channel sound system

A new speech/non-speech classification method using minimal Walsh basis functions

Implementation aspects of a novel speech packet loss concealment method

Emotional speech classification using Gaussian mixture models

A robust multichannel speech enhancement method based on decorrelation

Directional interpolation for field-sequential stereoscopic video

An efficient block motion estimation algorithm on multimedia processors

Efficient frame-level pipelined array architecture for full-search block-matching motion estimation

A locally adaptive subsampling algorithm for software based motion estimation

High performance error concealment algorithm by motion vector refinement for MPEG-4 video

Spatial error concealment based on directional decision and intra prediction

New block-based motion estimation for sequences with illumination variation and its application to video mosaicking

An efficient dual-interpolator architecture for sub-pixel motion estimation

Beyond the microscope: embedded detectors for cell biology applications

A digital CMOS DNA chip

Nanoliter array advances: miniaturized, high-speed PCR sensing & control

Retinal prosthesis device based on pulse-frequency-modulation vision chip

Image processing and interface for retinal visual prostheses

Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos

Development of an audio player as system-on-a-chip using an open source platform

Mapping system-on-chip designs from 2-D to 3-D ICs

Algorithm/architecture co-design of the generalized sampling theorem based de-interlacer [video signal processing]

Efficient DSP architecture for high-quality audio algorithms

An area-efficient and protected network interface for processing-in-memory systems

Optimal packet length with energy efficiency for wireless sensor networks

Multihop hello guided routing-reactive for mobile ad hoc networks

On performance of a charging/rewarding scheme in mobile ad-hoc networks

Effective division and merger of the autonomous clustering scheme for highly mobile large ad hoc networks

A simple address autoconfiguration mechanism for OLSR [MANET routing protocol]

A traffic aware, energy efficient MAC protocol for wireless sensor networks

A novel reseeding mechanism for pseudo-random testing of VLSI circuits

An embedded processor based SOC test platform

On the fault diagnosis in the presence of unknown fault models using pass/fail information

An analytical approach for soft error rate estimation in digital circuits

Electric field for detecting open leads in CMOS logic circuits by supply current testing

Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit

Economical passive filter synthesis using genetic programming based on tree representation

Symbolic small-signal analysis (SSA) tool

Accurate high frequency noise modeling in SiGe HBTs

Modeling of substrate noise block properties for early prediction

Carrier frequency offset estimation for OFDM systems

A novel post-nonlinear ICA-based reflectance model for 3D surface reconstruction

Blind separation of statistically independent signals with mixed sub-Gaussian and super-Gaussian probability distributions

Robust super-exponential methods for blind equalization of SISO systems with additive Gaussian noise

Necessary and sufficient conditions for LTI systems to preserve signal richness

A fuzzy algorithm for navigation of mobile robots in unknown environments

FPGA implementation of a recurrent neural fuzzy network for on-line temperature control

LMI-based neurocontroller for guaranteed cost control of uncertain time-delay systems

The use of NNs in MRAC to control nonlinear magnetic levitation system

BMI-based neurocontroller for state-feedback guaranteed cost control of discrete-time uncertain system

Architecture design of the re-configurable 2-D von Neumann cellular automata for image encryption application

Super-stable energy based switching control scheme for DC-DC buck converter circuits

Sliding-mode control design of parallel-connected switching converters for modular transformerless DC-AC step-up conversion

Integrated charge-control single-inductor dual-output step-up/step-down converter

Predictive valley current controller for two inductor buck converter

Boundary control of a bipolar square-wave generator using second-order switching surface

A pseudo-CCM buck converter with freewheel switching control

A cascade 3-1-1 multibit /spl Sigma//spl Delta/ A/D modulator with reduced sensitivity to non-idealities

A digital background calibration method for mash /spl Sigma/-/spl Delta/ modulators by using coefficient estimation

A novel semi-MASH sub-stage for high-order cascade sigma-delta modulators

A robust 3/sup rd/ order low-distortion multi-bit sigma-delta modulator with reduced number of op-amps for WCDMA

Analysis of clock jitter error in multibit continuous-time /spl Sigma//spl Delta/ modulators with NRZ feedback waveform

A low-power /spl Delta//spl Sigma/ modulator with low capacitor spread for multi-standard receiver applications

A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal

A current-mode ADC with adaptive quantization

Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS)

Switched-capacitor circuits using a single-phase scheme

An approach to an efficient reduction of the switching noise in switched-current circuits

A low-voltage low-distortion MOS sampling switch

A performance bound for a cascade LMS predictor

Application of radiation mode in desired sound field generation using loudspeaker array

A robust pitch estimation approach for colored noise-corrupted speech

Noisy autoregressive system identification by the ramp cepstrum of one-sided autocorrelation function

Artificial bandwidth extension of telephony speech by data hiding

Memory and computationally efficient psychoacoustic model for MPEG AAC on 16-bit fixed-point processors

Spectral correlation MUSIC algorithm for cyclostationary signals by exploitation of new array configuration

A frequency-domain SIR maximizing time-domain equalizer for VDSL systems

Low-power log-MAP turbo decoding based on reduced metric memory access

A design of orthogonal interleavers for multimodes turbo en-decoders

Efficient per-carrier channel equalizer for filter bank based multicarrier systems

Robustness analysis of a decision feedback generalized sidelobe canceller

Stability analysis for switched systems with continuous-time and discrete-time subsystems: a Lie algebraic approach

Stability analysis of pulse-width-modulated feedback systems with type 2 modulation: the critical case

Robust stabilization of control systems using piecewise linear Lyapunov functions and evolutionary algorithm

Observer synthesis for Lipschitz discrete-time systems

Stick-slip oscillations in resonant power converters

Double-bounded homotopy for analysing nonlinear resistive circuits

A framework for real time gesture recognition for interactive mobile robots

A method of 3D face recognition based on principal component analysis algorithm

Object tracking in video pictures based on image segmentation and pattern matching

Automatic video region-of-interest determination based on user attention model

Video segmentation using multiscale feature extraction and fusion

A 24 GHz dual-modulus prescaler in 90 nm CMOS

A new technique for design CMOS LNA for multi-standard receivers

An AC-coupled direct-conversion receiver for Global Positioning System

Design methodology for the optimization of transformer-loaded RF circuits

An 18 GHz low noise high linearity active mixer in SiGe

Variable-gain up-converter with current reuse for WCDMA wireless transmitters

An effective algorithm for delay constrained least cost unicast routing

Seamless roaming in wireless networks for video streaming

Packet scheduling based on Geo/sup Y//G//spl infin/ input process modeling for streaming video

A robust H.264 video streaming scheme for portable devices

A novel adaptive video playout control for video streaming over mobile cellular environment

Rate-distortion optimized video streaming with smooth quality constraint

High-order linear transformation MOSFET-C filters using operational transresistance amplifiers

Active RC filter with reduced capacitance by current division technique

Time-domain symmetry as criterion for band-pass equalizer design

Analog complex wavelet filters

Output noise of generalized high-order allpole OTA-C filters

10-th order programmable low-pass CMOS integrated pulse-shaping filter

An insensitive current mode universal biquad: multi-input multi-output

Low-sensitivity current-mode active-RC filters using impedance tapering

VLSI implementation of type-2 fuzzy inference processor

A power-driven multiplication instruction-set design method for ASIPs

A CORDIC processor with efficient table-lookup schemes for rotations and on-line scale factor compensations

Elimination of sign precomputation in flat CORDIC

Novel instructions and their hardware architecture for video signal processing

A novel reconfigurable architecture of low-power unsigned multiplier for digital signal processing

Design trade-offs in floating-point unit implementation for embedded and processing-in-memory systems

Implementation of a cycle by cycle variable speed processor

A hardware-based longest prefix matching scheme for TCAMs

A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms

A modified spiral search motion estimation algorithm and its embedded system implementation

HIBI-based multiprocessor SoC on FPGA

Dual use of power lines for data communications in a system-on-chip environment

A threshold-based algorithm and VLSI architecture of a K-best lattice decoder for MIMO systems

A 64-MHz/spl sim/1920-MHz programmable spread-spectrum clock generator

Reduction in spectral peaks of DC-DC converters using chaos-modulated clock

Nonlinear echo cancellation using an expanded correlation LMS algorithm

A ns-2 simulator utilizing chaotic maps for network-on-chip traffic analysis

Dynamics in a controlled flow model of a switching system

A performance estimation method for chaotic spread spectrum clock processes

Chaotification of nonlinear systems described by the fuzzy hyperbolic model

Experimental verification of 3-D hysteresis multi-scroll chaotic attractors

Cascading failures in scale-free coupled map lattices

Bifurcation and transitional dynamics in three-coupled oscillators with hard type nonlinearity

Bifurcation analysis of a circuit-related piecewise-affine map

On rigorous study of Poincare maps defined by piecewise linear systems [electronic circuit example]

A piecewise constant switched chaotic circuit with rect-rippling return maps

Observer-based approach for synchronization of a time-delayed, Chua's circuit

A fast bitplane combination algorithm for bitplane coded scalable image/video

Optimized decoding scheme for erroneous MPEG-4 FGS bitstream

A novel algorithm of spatial scalability for scrambled video

A low complexity architecture for binary image erosion and dilation using structuring element decomposition

Am object-based approach to plenoptic videos

Parameters estimation applied to automatic video processing algorithms validation

Fast pixel-based video scene change detection

Robust group-of-picture architecture for video transmission over error-prone channels

A novel interleaving algorithm for robust video transmission

A fast global motion estimation for moving objects segmentation using moment-preserving technique

Shot change detection on H.264/AVC compressed video

Algorithmic optimization of H.264/AVC encoder

Low complexity RDO mode decision based on a fast coding-bits estimation model for H.264/AVC

Viewpoint switching in multiview video streaming

A flexible macroblock ordering with 3D MBAMAP for H.264/AVC

CMOS sensor array for electrical imaging of neuronal activity

Integrated optical computing: system-on-chip for surface plasmon resonance imaging

Pulse modulation CMOS image sensor for bio-fluorescence imaging applications

CMOS contact imager for monitoring cultured cells

A CMOS capacitance sensor for cell adhesion characterization

Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations

Hierarchical instruction encoding for VLIW digital signal processors

Design of superscalar processor with multi-bank register file

Dynamic coarse grain dataflow reconfiguration technique for real-time systems design

Application specific instruction-set processor generation for video processing based on loop optimization

An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays

Fast 802.11 link adaptation for real-time video streaming by cross-layer signaling

A study of encoding and decoding techniques for syndrome-based video coding

Congestion-optimized scheduling of video over wireless ad hoc networks

A fast greedy algorithm for routing concurrent video flows

Image transmission over IEEE 802.15.4 and ZigBee networks

Integrated multi-objective cross-layer optimization for wireless multimedia transmission

A countermeasure against differential power analysis based on random delay insertion

Litho-driven layouts for reducing performance variability

Automatic monitor generation from regular expression based specifications for module interface verification

Power and delay analysis of 4:2 compressor cells

Timing error correction techniques for voltage-scalable on-chip memories

Incremental timing optimization for automatic layout generation

An FPGA based implementation of G.729

Fast estimation of area-delay trade-offs in circuit sizing

Performance analysis by topology indexed lookup tables

Optimized design of source coupled logic gates in GaAs HEMT technology

Initial solution for the optimum design delay equalizers

A novel approach for high-level power modeling of sequential circuits using recurrent neural networks

F-SEONS: a second-order frequency-domain algorithm for noisy convolutive source separation

A class of novel blind source extraction algorithms based on a linear predictor

New Riemannian metrics for improvement of convergence speed in ICA based learning algorithms

A class of space-time code for blind detection

Blind IQ error compensation in a direct conversion receiver for DVB-T

Recursive semi-blind decoding of a space-time block code over frequency-selective channel

Identification of road signs using a new ridgelet network

Hardware friendly vector quantization algorithm

A compact distance cell for analog classifiers

A learning algorithm for enhancing the generalization ability of support vector machines

Two-level decoupled Hamming network for associative memory under noisy environment

Pulse width modulator using a phase-locked loop variable phase shifter

Three-phase power factor corrector based on capacitor-clamped topology

Three-phase active power filter under unbalanced condition

A 36-V H-bridge driver interface in a standard 0.35-/spl mu/m CMOS process

Design of class E backlight module incorporating piezoelectric transformer

An integrated electronic ballast for small wattage high intensity discharge lamps

A 2-path bandpass sigma-delta modulator utilizing a 3-path structure

Digitally tuned bandpass sigma delta modulator for wireless communications

Design of continuous-time /spl Sigma//spl Delta/ modulators with sine-shaped feedback DACs

A tunable bandpass /spl Delta//spl Sigma/ modulator using double sampling

DAC compensation for continuous-time delta-sigma modulators

A 0.8V /spl Delta//spl Sigma/ modulator using DTMOS technique

Performance analysis of high-speed MOS transistors with different layout styles

An optimization technique for RF buffers with active inductors

Characterization of laser-induced photoexcitation effect on a surrounding CMOS ring oscillator

Calculation of intermodulation distortion in CMOS transconductance stage

A novel 1.5V DC offset cancellation CMOS down conversion mixer

Low voltage analog synthesizer of orthogonal signals: a current-mode approach

Improved design of fractional order differentiator using fractional sample delay

Digital differentiator design using fractional sample delay filter

Digital differentiators for narrow band applications in the lower to midband range

Variable multi-output passive digital filters

High tuning accuracy design of variable IIR filters as a cascade of identical sub-filters

A new cascaded modified CIC-cosine decimation filter

Correlation-based adaptive filters for channel identification

Generalized sidelobe cancellers with leakage constraints

Generalized partially adaptive concentric ring array

A subspace constrained constant modulus algorithm for blind array

A high-throughput DLMS adaptive algorithm

Canards in a slow-fast continuous piecewise linear vector field

Path following circuits - SPICE-oriented numerical methods where formulas are described by circuits $

Analysis of a hysteretic oscillator through a mixed time-frequency domain approach

On the identifiability of bilinear systems

Effects of variations of load distribution on network performance

On passivity enforcement for macromodels of S-parameter based tabulated subnetworks

Compressed-domain fall incident detection for intelligent home surveillance

Non-linear learning factor control for statistical adaptive background subtraction algorithm

An automated volumetric segmentation system combining multiscale and statistical reasoning

Perceived visual quality metric based on error spread and contrast

A unified probabilistic approach to face detection and tracking

A novel automatic white balance method for digital still cameras

Computationally efficient DOA estimation in a multipath environment using covariance differencing and iterative spatial smoothing

A test strategy for time-to-digital converters using dynamic element matching and dithering

A complete receiver solution for a chaotic direct-sequence spread spectrum communication system

A new method of an IF I/Q demodulator for narrowband signals

Experimental gigabit multidrop serial backplane for high speed digital systems

ASIC design of fast IP-lookup for next generation IP router

Baseball event detection using game-specific feature sets and rules

Wavelet transform to hybrid support vector machine and hidden Markov model for speech recognition

Effective shot boundary classification using video spatial-temporal information

An efficient method for face recognition under varying illumination

Event detection using multimodal feature analysis

Video shot segmentation using fusion of SVD and mutual information features

A CMOS bandgap voltage reference with absolute value and temperature drift trims

A very low drop voltage regulator using an NMOS output transistor

New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation

A single circuit solution for voltage sensors

Design considerations in bandgap references over process variations

A low-power digital PWM DC/DC converter based on passive sigma-delta modulator

A low voltage low 1/f noise CMOS bandgap reference

Observability analysis by measurement Jacobian matrix for state estimation

Recognition of power quality events using wavelet-based dynamic structural neural networks

Real-time phasor measurement for low frequency oscillation in power system

Evaluating performance of hybrid-type power system simulator based on transient stability analysis: a dynamical system approach

Fault location in automated distribution network

Signal waveform monitoring for power systems

On-line learning applied to power system transient stability prediction

A study on an ASIC design technique for digital protective relays

DBNS addition using cellular neural networks

Analog networks for mixed domain spatiotemporal filtering

A one-quadrant discrete-time cellular neural network architecture for pixel-level snakes: B/W processing

Selective similarity function for VLSI analog signal processing

A Gray-coded digital-to-analog converter for a mixed-mode processor array

Fixed-current method for programming large floating-gate arrays

Template design for binary-programmable cellular nonlinear networks

A complex texture classification algorithm based on Gabor-type filtering cellular neural networks and self-organized fuzzy inference neural networks

A beamforming method in UWB pulse array based on neural network

The modem for ultra-wideband communication employing surface-acoustic-wave devices

Using CLNS for FFTs in OFDM demodulation of UWB receivers

Dual drain-line distributed cell design for multi-Gbit/s transversal filter implementations

A systematic approach to CMOS low noise amplifier design for ultrawideband applications

Simple polar-loop transmitter for dual-mode Bluetooth

Functional modeling techniques for a wireless LAN OFDM transceiver

A multi-band multi-standard RF front-end IEEE 802.16a for IEEE 802.16a and IEEE 802.11 a/b/g applications

Transaction level modeling of IEEE 802.11 system

A concurrent multi-band LNA for multi-standard radios

An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications

Multiple description watermarking for lossy network

Directional watermarks in images

An error resilient image camouflaging scheme for secret image transmission

Semi-fragile watermarking for text document images authentication

Multiple description coding using multiple reference frame for robust video transmission

Digital watermarking for color video using a nonlinear filter in detection process

Image authentication using content based watermark

Hiding watermark in watermark [image watermarking]

A novel unequal error protection approach for error resilient video transmission

Optimal joint rate and power allocation in a multicell multimedia CDMA network

Audio signal segmentation and classification for scene-cut detection

Drift-free multiple description video coding with redundancy rate-distortion optimization

Optimized multiple description image coding using lattice vector quantization

Low redundancy layered multiple description scalable coding using the subband extension of H.264/AVC

Video error concealment by integrating dynamic programming and adaptive Kalman filtering techniques

Enhancing vocoder performance for music signals

An 8b 240 MS/s 1.36 mm/sup 2/ 104 mW 0.18 um CMOS ADC for DVDs with dual-mode inputs

Convergence analysis of a background interstage gain calibration technique for pipelined ADCs

Smart AD and DA converters

A low power and low voltage continuous time /spl Sigma//spl Delta/ modulator

Synthesis of sigma delta modulators employing continuous time delays

A low-voltage 3 mW 10-bit 4MS/s pipeline ADC in digital CMOS for sensor interfacing

Low-voltage micropower multipliers with reduced spurious switching

An area efficient 64-bit square root carry-select adder for low power applications

A low-power and high-throughput implementation of the SHA-1 hash function

Hyperblock formation: a power/energy perspective for high performance VLIW architectures

Ultra low voltage design considerations of SOI SRAM memory cells

Battery voltage prediction for portable systems

CPG-MTA implementation for locomotion control

A spiking silicon central pattern generator with floating gate synapses [robot control applications]

A bio-inspired CNN layer with image processing capabilities

Mismatch-tolerant CMOS oscillator and excitatory synapse for bioinspired image segmentation

Effect of mismatch on a ranked-order extractor array [image processing applications]

Parallel processor algorithm for variable block-size computation at low bitrates [video coding applications]

A Fourier series-based RLC interconnect model for periodic signals

Performance model for inter-chip communication considering inductive cross-talk and cost

RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction

High speed current-mode signaling circuits for on-chip interconnects

Capacitive coupling of data and power for 3D silicon-on-insulator VLSI

Accurate decoupling of capacitively coupled buses

Power-aware slack distribution for hierarchical VLSI design

A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation PART-I MOSFETs and CMOS inverters

Fast parameters optimization of an iterative decoder using a configurable hardware accelerator

Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis

CheckSyC: an efficient property checker for RTL SystemC designs

CRPG: a configurable random test-program generator for microprocessors

Optimal allocation of FACTS devices to enhance total transfer capability using evolutionary programming

Observed hybrid oscillations in an electrical distribution system

Power flow based allocation procedures for voltage security and transmission losses in deregulated power markets

Identification of chains of events leading to catastrophic failures of power systems

Using genetic algorithms for reliability calculations of complex power systems

Coordinated static stability margin management of inter-regional electricity systems

An ultrasonic filterbank with spiking neurons

Field test results for low power bearing estimator sensor nodes

High-sensitivity capacitive readout system for resonant submicrometer-scale cantilevers based sensors

AER EAR: a matched silicon cochlea pair with address event representation interface

A VLSI model of the bat dorsal nucleus of the lateral lemniscus for azimuthal echolocation

On the robustness of an analog VLSI implementation of a time encoding machine

A computer-based system to analyze neuron images

Automated dynamic cellular analysis in high throughput drug screens

A post-processing algorithm using histogram-driven anisotropic diffusion

A pixel-parallel anisotropic diffusion algorithm for subjective contour generation

Translation invariant combined denoising algorithm

A low dropout, CMOS regulator with high PSR over wideband frequencies

A new 4.3 ppm//spl deg/C voltage reference using standard CMOS process with 1V supply voltage

A sub-1V bandgap reference circuit using subthreshold current

Design methods for CMOS low-current finely tunable voltage references covering a wide output range

A new CMOS charge pump for low voltage applications

A dynamic start-up circuit for low voltage CMOS current mirrors with power-down support

A delay line based CMOS time digitizer IC with 13 ps single-shot precision

Discrete and continuous substrate noise spectrum dependence on digital circuit characteristics

High voltage tolerant output buffer design for mixed voltage interfaces

A practical BIST circuit for analog portion in deep sub-micron CMOS system LSI

Dither incorporated deterministic dynamic element matching for high resolution ADC test using extremely low resolution DACs

A two-step DDEM ADC for accurate and cost-effective DAC testing

A novel lattice structure of M-channel paraunitary filter banks

Multi-plet two-channel perfect reconstruction filter banks

Design of 2-channel linear phase filter bank: a lifting approach

A multiplierless filter bank with deep stopband suppression and narrow transition width

On a modified structure for cosine-modulated filter banks using the frequency-response masking approach

Factorization of a class of perfect reconstruction modified DFT filter banks with IIR filters

A new robust Kalman filter algorithm under outliers and system uncertainties

Adaptive beamforming using uniform concentric circular arrays with frequency invariant characteristics

A unified framework for least square and mean square based adaptive filtering algorithms

On reduced complexity IIR adaptive filters

Approximate QR-based algorithms for recursive nonlinear least squares estimation

A new block exact affine projection algorithm [acoustic echo cancellation system example]

A programmable floating-gate bump circuit with variable width

An integrated circuit chaotic oscillator and its application for high speed random bit generation

A macro-model for the efficient simulation of an ADC-based RNG

A low-power wideband frequency doubler in 0.18 /spl mu/m CMOS

Frame layer bit allocation for video transcoding

Efficient VLSI architecture for buffer used in EBCOT of JPEG2000 encoder

Localized weighted prediction for video coding

Frame-layer H.264 rate control improvement using Lagrange multiplier and quantizer

Optimal 2 sub-bank memory architecture for bit plane coder of JPEG2000

Motion-assisted rate control for ME/MC-based codecs [video coding]

Pulse generator design for UWB IR communication systems

Use of source degeneration for non-intrusive BIST of RF front-end circuits

A 1-V fully integrated CMOS frequency synthesizer for 5-GHz WLAN

Power optimized LC VCO and mixer co-design

2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer

Low-power high-Q NEMS receiver architecture

Steganalysis of data hiding in binary text images

A blind audio watermarking scheme using peak point extraction

Robust watermarking of music signals by cepstrum modification

Multipurpose image watermarking in DCT domain using subsampling

Programmable matched filter by charge-domain operation

Charge-domain FIR sampler with programmable filtering coefficients

Generalized quadrature bandpass sampling with FIR filtering

Minimal activity mixed-signal VLSI architecture for real-time linear transforms in video

A novel approach to the exact design of first- and second-order Bode-type variable-amplitude bilinear-LDI switched-capacitor equalizers

An adaptive analog synapse circuit that implements the least-mean-square learning rule

Bifurcation in parallel-connected buck converters under current-mode control

Analysis of series-parallel resonant converter with multipliers

Energy optimization of tapered buffers for CMOS on-chip switching power converters

Multi-mode controller CMOS integrated circuit for switching power converters

A multi-level inverter for driving a high voltage display

From architecture to implementation of a wireless, multiple antenna testbed

Nonlinear state-space model of charge-pump based frequency synthesizers

Channel estimation for a new high performance MIMO STC-OFDM WLAN system

Novel digital signal processing unit for Ethernet receiver

Joint compensation of IQ-imbalance and carrier phase synchronization errors in communication receivers

An all-digital data recovery circuit optimization using Matlab/Simulink

A scalable pipelined complex valued matrix inversion architecture

Testing system for measuring and calibrating the transmission power of EDGE mobiles

Rapid signal acquisition for low-rate carrier-based ultra-wideband impulse radio

On the signed-binary window method [cryptosystem applications]

A low-complexity iterative interference suppressor for coded aperiodic spreading CDMA systems

Simulink based model realization for CDMA communication over power lines

Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders

An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264

Performance-driven optimization for video accelerator design [video coding]

A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC

An AMBA-compliant deblocking filter IP for H.264/AVC

Timer based scheduling control algorithm in WLAN for real-time services

A novel MPEG-4 rate control method with spatial resolution conversion for low bit-rate coding

A low-power motion compensation IP core design for MPEG-1/2/4 video decoding

A 3-way SIMD engine for programmable triangle setup in embedded 3D graphics hardware

An MPEG-4 IPMPX design and implementation on MPEG-21 test bed

VLSI architecture of low memory and high speed 2D lifting-based discrete wavelet transform for JPEG2000 applications

A new motion compensation design for H.264/AVC decoder

DCT-domain image registration techniques for compressed video

Architectures for analog motion estimation processors: a comparison

An 11M-triangles/sec 3D graphics clipping engine for triangle primitives

A 33.2M vertices/sec programmable geometry engine for multimedia embedded systems

A two-way SIMD-based reconfigurable computing architecture for multimedia applications

A new scene change feature for video transcoding

A new cubic rate distortion model for low-delay video communication

A robust shot change detection method for content-based retrieval

TV commercial detection in news program videos

Autonomous learning of visual concept models

A fixed-point 3D graphics library with energy-efficient cache architecture for mobile multimedia systems

A frequency domain equalizer for WLAN 802.11g single-carrier transmission mode

Wavelet based fingerprint image enhancement

Technology scaling impact on embedded ADC design for telecom receivers

Power consumption issues in high-speed high-resolution pipelined A/D converters

A 10-bit 400-MS/s 170 mW 4-times interleaved A/D converter in 0.35-/spl mu/m BiCMOS

An embedded 12-bit 80MS/s A/D/A interface for power-line communications in 0.13 /spl mu/m pure digital CMOS technology

Process tolerant design of N-tone /spl Sigma//spl Delta/ converters

A new CAM based S/S/sup -1/-box look-up table in AES

An efficient architecture for the AES mix columns operation

A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher

A new RSA encryption architecture and hardware implementation based on optimized Montgomery multiplication

Efficient multi-prime RSA immune against hardware fault attack

AES crypto chip utilizing high-speed parallel pipelined architecture

Performance of finite iteration DTCNN with truncated stationary templates [digit recognition example]

An algorithm for predicting the steady state behavior of binary CNNs

Global exponential stability analysis of delayed cellular neural networks

On global dynamic behavior of weakly connected cellular nonlinear networks

On complete stability of three-cell CNNs with opposite-sign templates

Complex dynamics in a class of nearly-symmetric competitive CNNs

Ultra-low power flip-flops for MTCMOS circuits

Design techniques for low-power cascaded CML gates

A low-power and high-speed quaternary interconnection link using efficient converters

Energy-saving design technique achieved by latched pass-transistor adiabatic logic

A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits

More than two orders of magnitude leakage current reduction in look-up table for FPGAs

Generation and properties of new fastest linearly independent transforms over GF(2) with reordering

Properties and relations of ternary linearly independent transforms [multivalued logic applications]

Analysis of power consumption in VLSI global interconnects

A divide-and-conquer approach to estimating minimum/maximum leakage current

Synthesis for regularity using decision diagrams [logic IC synthesis and layout]

Multiple project wafers for medium-volume IC production

A study on distribution network planning with considering customer's utilization of distributed generators

Three-phase power flow for FRIENDS network

An agent approach to power system distribution networks

A distributed slack bus model and its impact on distribution system application techniques

Variable neighborhood tabu search for capacitor placement in distribution systems

A new approach of hierarchical optimization to distribution system service restoration

A low-power visual horizon estimation chip

A spatial variance approach to target tracking with sensor arrays

A 8-/spl mu/W, 0.3-mm/sup 2/ RF-powered transponder with temperature sensor for wireless environmental monitoring

FPGA implementation of a CDMA source coding and modulation subsystem for a multiband fluorometer with pattern recognition capabilities

A 1V current-mode CMOS active pixel sensor

Sonar echo-location in 2-D using mini-microphone array and spatiotemporal frequency filtering

Smart bio-laboratories of the future

A conceptual discussion on relationship between vergence and conjugate eye movements on the viewpoint of system and control engineering

Dynamic sub-cellular behavior study in high content imaging using a multi-threshold approach

Cooperative dynamics coordinated by stochastic noise in a multi-cell system

CMOS readout and control architecture for single-cell real-time microsystems

A reconfigurable architecture for scanning biosequence databases

Active-RC channel selection filter tunable from 6 kHz to 18 MHz for software-defined radio

A 5 GHz sub-harmonic direct down-conversion mixer for dual-band system in 0.35 /spl mu/m SiGe BiCMOS

An optimized 2.4 GHz CMOS LC-tank VCO with 0.55 %/V frequency pushing and 516 MHz tuning range

A 5GHz to 6GHz integrated differential LNA

A low distortion, current feedback, programmable gain amplifier

A high-speed wide-range low-distortion constant-gm cell design for GHz applications

A low power block-matching analog motion estimation processor

A cost-effective histogram test-based algorithm for digital calibration of high-precision pipelined ADCs

An N/sup th/ order central symmetrical layout pattern for nonlinear gradients cancellation

A flexible ADC approach for mixed-signal SoC platforms

Techniques for sensitizing RF path under SER test

A 0.18 /spl mu/m-CMOS near-end crosstalk (NEXT) noise canceller utilizing tunable active filters for 4-PAM/20Gbps throughput backplane channels

Perfect tracking control using multirate control in magnetic levitation system

New graph transformation schemes in graph-based memory allocation method for an indirect addressing DSP

A complete spurs distribution model for direct digital period synthesizers

An evaluation of a hybrid-logarithmic number system DCT/IDCT algorithm [image compression applications]

Efficient realization for symmetric orthogonal multiwavelet by simple scaling and rotation

Integration of image stabilizer with video codec for digital video cameras

An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications

Fully-differential 13 Gbps clock recovery circuit for OC-255 SONET applications

Clock and data recovery with adaptive loop gain for spread spectrum SerDes applications

A delay compensation technique for n-phase clock generation with 2(N-1) delay units

A family of SiGe quadrature oscillators for microwave applications

High speed pilot-less sampling frequency acquisition for DMT systems

Approximate stationary density of the nonlinear dynamical systems excited with white noise

Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits

A method for searching multiple local optimal solutions of nonlinear optimization problems

An efficient homotopy method for finding DC operating points of nonlinear circuits

SVD-based approximations of bivariate functions

A design method for parallel recursive least square adaptive Volterra filter

A content adaptive de-interlacing algorithm [video signal processing applications]

A low complexity motion compensated frame interpolation method

Restoration method of missing areas in still images using GMRF model

A new homomorphic Bayesian wavelet-based MMAE filter for despeckling SAR images

An adaptive edge-preserving artifacts removal filter for video post-processing

Bayesian algorithm for video noise reduction in the wavelet domain

A 53.3 Mb/s 4/spl times/4 16-QAM MIMO decoder in 0.35-/spl mu/m CMOS

Adaptive filtering-based iterative channel estimation for MIMO wireless communications

Performance analysis for MIMO systems using zero forcing detector over Rice fading channel

Parallelism/regularity-driven MIMO detection algorithm design

A new reduced-complexity sphere decoder with true lattice-boundary-awareness for multi-antenna systems

Degradation on the performance of MIMO system under a correlated sub-channels condition

Formatted text document data hiding robust to printing, copying and scanning

Shadow watermark embedding system

Adaptive watermarking using relationships between wavelet coefficients

Layered access control schemes on watermarked scalable media

Quantization-based image steganography without data hiding position memorization

Digital watermarking using Walsh code sequences with error spreading technique and intra-pixel prediction

A novel method of lossy image compression for digital image sensors with Bayer color filter arrays

Realization of card-centric framework: a card-centric computer [smart cards]

Error vector magnitude (EVM) measurements for GSM/EDGE applications revised under production conditions

A phase locked loop with a mixed mode loop filter for clock/data recovery in optical disc drives

A 3D mouse for interacting with virtual objects

A robust embedded software platform for versatile camera systems

Design of an efficient memory-based DVB-T channel decoder

A new high gain low voltage 1.45 GHz CMOS mixer

A new 5 GHz CMOS dual-modulus prescaler

A wide tuning range, 1 GHz-2.5 GHz DLL-based fractional frequency synthesizer

A 23 GHz high isolation sub-harmonic mixer

A current mode 2.4 GHz direct conversion receiver

An integrated pseudo-noise code acquisition processor for WCDMA, CDMA2000 and 802.11b systems

Derivation of two- and three-branch lumped element codirectional couplers and their frequency characteristics

Low-complexity adaptive algorithms for pre-distortion of power amplifiers

A low-power distributed wide-band LNA in 0.18 /spl mu/m CMOS

IIP2 calibration methods for current output mixer in direct-conversion receivers

A low power CMOS low noise amplifier for ultra-wideband wireless applications

Design of an ultra-wideband low noise amplifier in 0.13 /spl mu/m CMOS

Modeling of MOS varactors and characterizing the tuning curve of a 5-6 GHz LC VCO

Ultra low power RF section of a passive microwave RFID transponder in 0.35 /spl mu/m BiCMOS

A 0.8 V 5.9 GHz wide tuning range CMOS VCO using inversion-mode bandswitching varactors

Modeling power amplifiers with antenna mismatch

A gigahertz wideband CMOS multiplier for UWB transceiver

A high-frequency phase-compensation fractional-N frequency synthesizer

A 13.56 MHz RFID transponder front-end with merged load modulation and voltage doubler-clamping rectifier circuits

A 6-10-GHz ultra-wideband tunable LNA

Accurate performance prediction of multi-GHz CML with data run-length variations

A wideband CMOS LNA design approach

A low-power CMOS power amplifier for ultra wideband (UWB) applications

A new gain controllable on-chip active balun for 5 GHz direct conversion receiver

Development of the FES system with neural network + PID controller for the stroke

Noisy speech recognition by hierarchical recurrent neural fuzzy networks

Thunderstorm tracking system using neural networks and measured electric fields from few field mills

Neuro-sliding mode control for magnetic levitation systems

A new time-variant neural based approach for nonstationary and non-linear system identification

Natural gradient for minor component extraction

Exploiting application locality to design fast, low power, low complexity neural classifiers

Neural network handoff in shadow-Rayleigh fading

Form specifies function: robust spike-based computation in analog VLSI without precise synaptic weights

Hardware-based support vector machine classification in logarithmic number systems

Fuzzy logic based handover in MC-CDMA system

Intelligent ultra fast charger for Ni-Cd batteries

Extending SystemC to support mixed discrete-continuous system modeling and simulation

IBMG: interpretable behavioral model generator for nonlinear analog circuits via canonical form functions and genetic programming

Behavioural modeling and simulation of a switched-current phase locked loop

Modeling and simulation of mixed signal systems using a multi-lingual simulator

Behavioural modelling, simulation, test and diagnosis of MEMS using ANNs

Ascend: automatic bottom-up behavioral modeling tool for analog circuits

Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT

Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity

A partial parallel algorithm and architecture for arithmetic encoder in JPEG2000

CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]

Encoding circuits for low power optical on-chip communications

Error-tolerant FIR filters based on low-cost residue codes

Climbing obstacles via bio-inspired CNN-CPG and adaptive attitude control

Recent results on the prediction of EEG signals in epilepsy by discrete-time cellular neural networks (DTCNN)

Retina model with real time implementation

Towards an implantable ultra-low power biochemical signal processor for blood and tissue monitoring

Self-organized cortical map formation by guiding connections

An efficient model for performance analysis of asynchronous pipeline design methods

Low energy asynchronous architectures

Convergent micro-pipelines: a versatile operator for mixed asynchronous-synchronous computations

Measurement of delay mismatch due to process variations by means of modified ring oscillators

A memory controller that reduces latency of cached SDRAM

Concurrent algorithm for high-speed point multiplication in elliptic curve cryptography

Energy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications

Opcode encoding for low power embedded systems

Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique

A runtime auto scalable power-efficient instruction-cache design

Low power commutator for pipelined FFT processors

A low-power scan-path architecture

Extension of observability analysis to Hachtel's augmented matrix [power system analysis applications]

A smooth power flow model of electric power system with generator reactive power limits taken into consideration

Optimal procurement of VAR ancillary service in the electricity market considering voltage security

Unsolvable power flow - restoring solutions of the electric power network equations

Damping improvement through tuning controller limits of a series FACTS device

Applications of operational transconductance amplifier in power system analog emulation

A low power CMOS imager based on time-to-first-spike encoding and fair AER

Self-powered active pixel sensors for ultra low-power applications

A 128/spl times/128 floating gate imager with self-adapting fixed pattern noise reduction

A 80 /spl mu/W/frame 104/spl times/128 CMOS imager front end for JPEG compression

A CMOS image sensor for focal plane decomposition

CMOS image sensor with watermarking capabilities

Field test of the world first 200 Mbps PLC modems

QoS technologies on AV/CE-oriented wireless home network

Is home network application acceptable or not?

New architecture of realizing seamless connectivity and cooperative control for home network systems

3D sound movement system for embedded applications

SH-mobile - low power application processor for cellular [3G cellular phones]

A wide-band low-noise amplifier with double loop feedback

An interference rejection filter for an ultra-wideband quadrature downconversion autocorrelation receiver

A read-out strategy and circuit design for high frequency MEMS resonators

A low-power switched-current CDMA matched filter employing MOS-linear matching cell and output A/D converter

A re-configurable high-speed CMOS track and latch comparator with rail-to-rail input for IF digitization [software radio receiver applications]

Fast-switching adaptive bandwidth frequency synthesizer using a loop filter with switched zero-resistor array

Fully integrated charge sensitive amplifier for readout of micromechanical capacitive sensors

Fully integrated charge pump for high voltage excitation of a bulk micromachined gyroscope

Flexible high-accuracy wide-range gas sensor interface for portable environmental nosing purpose

Adaptive sensor response correction using analog filter compatible with digital technology [load cell sensor applications]

A modular RC-active network for vibration damping in piezo-electro-mechanical beams

Cost effective high voltage driver for large channel count optical MEMS switch applications

Face segmentation based on Hue-Cr components and morphological technique

A combined interpolatorless interpolation and high accuracy sampling process for digital class D amplifiers

Time-delay direction finding based on canonical correlation analysis [electronic warfare applications]

DWT domain multi-matcher on-line signature verification system

Digital system for detection and classification of electrical events

Tap selection based MMSE equalization for high data rate UWB communication systems

Design of UWB pulses based on B-splines

Optimizing vertical common subexpression elimination using coefficient partitioning for designing low complexity software radio channelizers

A BPSK demodulator circuit using an anti-parallel synchronization loop

Novel systolic array architecture for the decorrelator using conjugate gradient for least squares algorithm

An efficient pre-traceback approach for Viterbi decoding in wireless communication

Bifurcation analysis of on-chip LC VCOs

A scalable DCO design for portable ADPLL designs

A 2.5GHz phase-switching PLL using a supply controlled 2-delay-stage 10GHz ring oscillator for improved jitter/mismatch

A 360/spl deg/ extended range phase detector for type-I PLLs

A two-chip, 4-MHz, microelectromechanical reference oscillator

A study of injection locking in ring oscillators

One-pass computation-aware motion estimation with adaptive search strategy

A framework for fine-granular computational-complexity scalable motion estimation [real-time video coding applications]

Fast sub-pixel inter-prediction - based on texture direction analysis (FSIP-BTDA) [video coding applications]

Efficient search and mode prediction algorithms for motion estimation in H.264/AVC

Efficient video motion estimation using dual-cross search algorithms

Rapid block-matching motion estimation using modified diamond search algorithm

Current mode multi-level simultaneous bidirectional I/O scheme for chip-to-chip communications

Algorithm for peak to average power ratio reduction operating at symbol rate

A 3.5-Gb/s CMOS burst-mode laser driver with automatic power control using single power supply

Common-mode stability in low-power LO drivers

An application-level methodology to guide the design of intelligent-processing, power-aware passive RFIDs

On the implementation of 128-pt FFT/IFFT for high-performance WPAN

Near-perfect cover image recovery anti-multiple watermark embedding approaches

Privacy preserving data mining with unidirectional interaction

Progressive scrambling for MP3 audio

Averaging attack resilient video fingerprinting

Multimedia data encryption via random rotation in partitioned bit streams

A new visual cryptography using natural images

Digital self-correction of time-interleaved ADCs

Automated design of a 10-bit, 80MSPS WLAN DAC for linearity and low-area

An analog-to-digital converter with Golomb-Rice output codes

10-bit programmable voltage-output digital-analog converter

A background correction technique for timing errors in time-interleaved analog-to-digital converters

Feedforward-type parasitic capacitance canceler and its application to 4 Gb/s T/H circuit

Synthesis of hybrid filter banks by global frequency domain least square solving

Implementation of a novel read-out strategy based on a Wilkinson ADC for a 16/spl times/16 pixel X-ray detector array

A 12-B 10-msamples/s CMOS switched-current delta-sigma modulator

A 1.5V multirate multibit sigma delta modulator for GSM/WCDMA in a 90 nm digital CMOS process

Time-interleaved multirate sigma-delta modulators

A direct synthesis method of cascaded continuous-time sigma-delta modulators

A sixth-order subsampling continuous-time bandpass delta-sigma modulator

High-order single-loop double-sampling sigma-delta modulator topologies for broadband applications

Adaptive processing applied to the design of highly digital analog interfaces

Spurious tone free digital delta-sigma modulator design for DC inputs

Towards a rigorous formulation of the space mapping technique for engineering design

Behavioral modeling simulation and high-level synthesis of pipeline A/D converters

Delay modeling of CMOS/CPL logic circuits

Ground bounce calculation due to simultaneous switching in deep sub-micron integrated circuits

Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC

A high-level dynamic-error model of a pipelined analog-to-digital converter

An explorative tile-based technique for automated constraint transformation, placement and routing of high frequency analog filters

A formal approach to the slack driven scheduling problem in high-level synthesis

Design of MOS current mode logic gates - computing the limits of voltage swing and bias current

Interconnect delay optimization via high level re-synthesis after floorplanning

Using symbolic computer algebra for subexpression factorization and subexpression decomposition in high level synthesis

BDD decomposition for mixed CMOS/PTL logic circuit synthesis

FPGA technology mapping optimization by rewiring algorithms

A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR gate and the CMOS NAND gate

Domain fault model and coverage metric for SoC verification

Validation analysis and test flow optimization of VLSI chip

Deterministic and low power BIST based on scan slice overlapping

Modeling and formal verification of dataflow graph in system-level design using Petri net

A robust and correct computation for the curvilinear routing problem

Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs

Instruction-based delay fault self-testing of pipelined processor cores

Gradient-based methods for simultaneous blind separation of mixed source signals

Blind identification of brain mechanism in MEG

Chaotic signal separation from a linear mixture

Blind identification of MIMO channels with periodic modulation

Blind low rate multiuser detection for multirate multicarrier CDMA systems using antenna array

DOA-matrix decoder for STBC-MC-CDMA systems over frequency-selective channel

An ICA based approach for blind deconvolution of three-dimensional signals

Evaluating a blind channel estimation technique that uses a hardware efficient equalizer

A consideration of blind source separation using wavelet transform

An approach for nonlinear blind source separation of signals with noise using neural networks and higher-order cumulants

Subband blind equalization using wavelet filter banks

Audio source separation by source localization with Hilbert spectrum

Uplink channel estimation for space-time block coded multiple-input multiple-output MC-CDMA systems

An alternative natural gradient approach for multichannel blind deconvolution

Decision feedback equalizer with the blind matched filter estimation

Integrated blind electronic equalizer for fiber dispersion compensation

Linear and nonlinear macromodels for power/signal integrity

Delay extraction from frequency domain data for causal macro-modeling of passive networks

Passive approximation of tabulated frequency-data by Fourier expansion method

Noise generation, coupling, isolation, and EM radiation in high-speed package and PCB

Accurate and closed-form SPICE compatible passive macromodels for distributed interconnects with frequency dependent parameters

Modeling of power distribution networks with signal lines for SPICE simulators

Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation

Quantized LDPC decoder design for binary symmetric channels

Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes

An analog/digital mode-switching LDPC codec

Digital VLSI OFDM transceiver architecture for wireless SoC design

A one-quadrant discrete-time cellular neural network CMOS chip for pixel-level snakes

Various implementations of topographic, sensory, cellular wave computers

Implementation of SIMD vision chip with 128/spl times/128 array of analogue processing elements

Dynamically coupled multi-layer mixed-mode CNN

Spatiotemporal pattern formation in the ACE16k CNN chip

CNN wave based computation for robot navigation on ACE16K

A single-chip FPGA design for real-time ICA-based blind source separation algorithm

Design and FPGA implementation of finite Ridgelet transform [image processing applications]

A novel metric representation for low-complexity log-MAP decoder

Gradient pile up for edge detection on hardware

Area-efficient systolic architectures for inversions over GF(2/sup m/)

A speech recognizer with selectable model parameters

Reconfigurable multiple scan-chains for reducing test application time of SOCs

The improvement for transaction level verification functional coverage

Parallely testable design for detection of neighborhood pattern sensitive faults in high density DRAMs

Efficient power model for crossbar interconnects

Coupling reduction analysis of bus-invert coding

Energy and latency evaluation of NoC topologies

An adaptive super-exponential deflation algorithm for blind deconvolution of MIMO systems using the matrix pseudo-inversion lemma

Filterbank-based blind signal separation with estimated sound direction

Blind signal separation into groups of dependent signals using joint block diagonalization

Blind extraction of a dominant source from mixtures of many sources using ICA and time-frequency masking

Independent arrays or independent time courses for gene expression time series

Blind separation of a class of nonlinear ICA models

A novel application specific network protocol for wireless sensor networks

High-efficiency power amplifier for wireless sensor networks

A new switched capacitor circuit for parallel-pixel image processing [vision sensor integrated signal processing]

Broadband dielectric spectroscopy CMOS readout circuit for molecular sensing

Read-out circuit in RT-fluxgate

Integrated interface circuits for chemiresistor arrays

SHD movie distribution system using image container with 4096/spl times/2160 pixel resolution and 36 bit color

An implementation of JPEG 2000 interactive image communication system

Designing and packaging technology of Renesas SIP

System LSI design with C-based behavioral synthesis and verification

Approach for physical design in sub-100 nm era

An advance RTL to GDS2 design methodology for 90 nm and below system LSIs to solve timing closure, signal integrity and design for manufacturing

CMOS high-linear wide-dynamic range RF on-chip filters using Q-enhanced LC filters

70 MHz CMOS gm-C IF filter

Voltage-mode high-order OTA-only-without-C low-pass (from 215 M to 705 M Hz) and band-pass (from 214 M to 724 M Hz) filter structure

Application of reverse-active npns for compact, wide-tuning f/sub T/-integration-based filters in SiGe HBT BiCMOS technology

A 2 V 0.25 /spl mu/m CMOS 250 MHz fully-differential seventh-order equiripple linear phase LF filter

Analysis of traveling wave and transversal analog adaptive equalizers

Rules for systematic synthesis of all-transistor analogue circuits by admittance matrix expansion

Fast iterative method package for high frequency circuits analysis

Mixed signal and SoC design flow requirements

Analog VLSI circuit-level synthesis using multi-placement structures

Improved modeling of sigma-delta modulator non-idealities in Simulink

Analysis of supply and ground noise sensitivity in ring and LC oscillators

Multichannel SVD-based image de-noising

Analysis of nonlinear residual echo suppressors for telecommunications [voice communication applications]

SMF robust filtering in impulsive noise

Modelling of high-order mechanical plate vibration systems by multidimensional wave digital filters

A cost-effective memory-based real-valued FFT and Hermitian symmetric IFFT processor for DMT-based wire-line transmission systems

Defining correlation functions and power spectra for multirate random processes

Pilot tone design for peak-to-average power ratio reduction in OFDM

High-speed and low-power design of parallel turbo decoder

Efficient view maintenance in wireless networks [mobile database view maintenance applications]

Digital signal processing engine design for polar transmitter in wireless communication systems

A novel technique for I/Q imbalance and CFO compensation in OFDM systems

Architectural issues in base-station frequency synthesizers

Integral observer approach for chaos synchronization with transmission disturbances

Synchronizing chaotic Colpitts circuits adaptively with parameter mismatches and channel distortions

Synchronization in an array of chaotic systems coupled via a directed graph

A subtle link in switched dynamical systems: saddle-node bifurcation meets border collision

Bifurcation and transitional dynamics in asymmetrical two-coupled oscillators with hard type nonlinearity

Bifurcations in modified BVP neurons connected by inhibitory and electrical coupling

Error sensitivity testing for the MC-EZBC scalable wavelet video coder

A model-based rate allocation mechanism for wavelet-based embedded image and video coding

Optimal resynchronization for layered video over wireless channel

Sub-sequence video coding for improved temporal scalability

Scalable multiview video coding using wavelet

Stereo video coding system with hybrid coding based on joint prediction scheme

A generalized semi-blind channel estimation for pilot-aided OFDM systems

Jitter limitations on multi-carrier modulation

Estimating the fading coefficient in mobile OFDM systems using state-space model

Block-wise adaptive modulation for OFDM WLAN systems

A hybrid space-time and collaborative coding scheme for wireless communications

An analog modulator/demodulator using a programmable arbitrary waveform generator

A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding

A hardware-based predictive motion estimation algorithm

A multiplication-accumulation computation unit with optimized compressors and minimized switching activities

A cost-effective media processor for embedded applications [audio decoder example]

Design and implementation of a new cryptographic system for multimedia transmission

Low-cost implementation of a super-resolution algorithm for real-time video applications

A 0.35 /spl mu/m CMOS comparator circuit for high-speed ADC applications

A 4-bit 5 GS/s flash A/D converter in 0.18 /spl mu/m CMOS

A low-power 4-b 2.5 Gsample/s pipelined flash analog-to-digital converter using differential comparator and DCVSPG encoder

A 1.2 GHz adaptive floating gate comparator with 13-bit resolution

An 8-bit 160 MS/s folding-interpolating ADC with optimized active averaging/interpolating network

Offset compensation in flash ADCs using floating-gate circuits

A novel approach for implementing ultra-high speed flash ADC using MCML circuits

A 1.8 V 3.2 /spl mu/W comparator for use in a CMOS imager column-level single-slope ADC

Design considerations of a floating-point ADC with embedded S/H

A new CCII-based pipelined analog to digital converter

A 12 bits/200 MHz resolution/sampling/power-optimized ADC in 0.25 /spl mu/m SiGe BiCMOS

A low power pipelined analog-to-digital converter using series sampling capacitors

A generic multilevel multiplying D/A converter for pipelined ADCs

A 10-bit algorithmic A/D converter for cytosensor application

An adaptive, truly background calibration method for high speed pipeline ADC design

The realization of a mismatch-free and 1.5-bit over-sampling pipelined ADC

An 800 Mbps system interconnect modeling and simulation for high speed computing

Ternary Walsh transform

A post layout watermarking method for IP protection

Rapid and precise instruction set evaluation for application specific processor design

Modem floorplanning with abutment and fixed-outline constraints

Modeling of MOS transistors based on genetic algorithm and simulated annealing

VLSI block placement with alignment constraints based on corner block list

Multiobjective VLSI cell placement using distributed simulated evolution algorithm

A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation

A new congestion and crosstalk aware router

Fast integer linear programming based models for VLSI global routing

Floorplanning with clock tree estimation

Segmented channel routing with pin rearrangements via satisfiability

An automatic face recognition system based on wavelet transforms

Hardware realization of panoramic camera with speaker-oriented face extraction for teleconferencing

A novel content-adaptive interpolation

Arbitrary scale image enlargement with the prediction of high frequency components

Restoration from image degraded by white noise based on iterative spectral subtraction method

Compensation of errors generated by an analog 2D DCT

An optimal tone reproduction curve operator for the display of high dynamic range images

The FIR filter bank with given analysis filters that minimizes various worst-case measures of error at the same time

Directionally weighted color interpolation for digital cameras

A novel color interpolation algorithm by pre-estimating minimum square error

A random-valued impulse noise detector using level detection

Super-resolution image restoration from blurred observations

A nearest neighbor graph based watershed algorithm

JPEG 2000 encryption enabling fine granularity scalability without decryption

DSVD: a tensor-based image compression and recognition method

Approximate treatment for calculation of the rate-distortion slope in EBCOT

A simplified algorithm of JPEG2000 rate control for VLSI implementation

Quality improvement technique for JPEG images with fractal image coding

A scalable encryption method allowing backward compatibility with JPEG2000 images

Lossless implementation of Motion JPEG2000 integrated with invertible deinterlacing

Improved fast encoding method for vector quantization based on subvector technique

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.

The IEEE International Symposium on Circuits and Systems, 2003. Tutorial Guide: ISCAS 2003.

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)

Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97

1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

1993 IEEE International Symposium on Circuits and Systems

[Proceedings] 1992 IEEE International Symposium on Circuits and Systems

1991., IEEE International Sympoisum on Circuits and Systems

IEEE International Symposium on Circuits and Systems

IEEE International Symposium on Circuits and Systems,

1988., IEEE International Symposium on Circuits and Systems

Minimizing power with flexible voltage islands

Content Provider	IEEE Xplore Digital Library
Author	Puri, R. Kung, D. Stok, L.
Copyright Year	2005
Description	Author affiliation: IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA (Puri, R.; Kung, D.; Stok, L.)
Abstract	Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASIC offer the best power efficiency for high-performance applications. The flexibility of ASIC allow for the use of multiple voltages and multiple thresholds to match the performance of critical regions to their timing constraints, and minimize the power everywhere else. The use of multiple supply voltages presents some unique physical and electrical challenges. Level shifters need to be introduced between the various voltage regions. The physical layout needs to be designed to ensure the efficient delivery of the correct voltage to various voltage regions. More flexibility can be gained by using appropriate level shifters.
Starting Page	21
Ending Page	24
File Size	157003
Page Count	4
File Format	PDF
ISBN	0780388348
DOI	10.1109/ISCAS.2005.1464514
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage Application specific integrated circuits Circuit synthesis Logic
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in