NDLI: Dedicated readout ASIC for dual modality probe

Content Provider	IEEE Xplore Digital Library
Author	Galasso, M. Orsolini Cencelli, V. Fabbri, A. Bennati, P. Cinti, M.N. Pani, R. De Notaristefani, F.
Copyright Year	2013
Description	Author affiliation: Dept. Mol. Med., Sapienza Univ., Rome, Italy (Cinti, M.N.) \|\| INFN Ist. Naz. di Fis. Nucleare Rome, Rome, Italy (Galasso, M.; Orsolini Cencelli, V.; Fabbri, A.; Bennati, P.; Pani, R.; De Notaristefani, F.)
Abstract	The bimodal diagnostic systems like ultrasound/scintigraphic ones have the benefit of providing both morphological and physiological information. In the case in which it intends to develop a compact bimodal probe it is important that, as the readout electronics are doubled, the acquisition system is the most compact possible. In this paper we present the characterization and preliminary measurements on a multi-channel readout ASIC for PSPMTs. The chip is equipped with 32 readout channels, as different works show that single channel readout allows to exploit the performances of a gamma detector, especially for linearity. Each single channel readout is composed by a variable capacitor CSA, a sample&hold and a variable gain amplifier (VGA). The possibility to change the gain of the amplifier allows to compensate for the differences in gain of the anodes of the PSPMT, while the possibility of changing the integrator capacitor allows to adapt the input dynamic of the chip depending on the PMT used (BA or SBA photocatode) and on the scintillation crystal coupled to the PMT itself. The preliminary measurements show that a 200 kHz maximum sampling rate is achievable, with 1 V input dynamic and an overall linearity of the whole channel with respect to the input charge impulse of than 2%. To validate the performances of the ASIC different operative measurement was made in two configurations: with a single chip and two R11265-M16 PMTs, and, parallelizing two chips with a single PMT H8500. The tubes were coupled with scintillation crystals with different response speeds, from CsI to LaBr3.
Starting Page	1
Ending Page	6
File Size	341510
Page Count	6
File Format	PDF
e-ISBN	9781479905348
DOI	10.1109/NSSMIC.2013.6829779
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-27
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitors Linearity Application specific integrated circuits Semiconductor device measurement Voltage measurement Switches Probes
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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