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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Calvet, D. |
| Copyright Year | 2013 |
| Description | Author affiliation: Inst. de Rech. sur les lois Fondamentales de l'Univers, CEA Saclay, Gif-sur-Yvette, France (Calvet, D.) |
| Abstract | This paper presents the design and performance of a new readout system for gaseous and silicon detectors built for the Minos nuclear physics experiment. A major constraint was to provide a multi-thousand channel, high performance readout system with low manpower effort and tight cost. This was achieved by the re-use of some earlier ASIC and front-end card (FEC) developments, the design of a new digital readout card, called the Feminos, and the use of commercial off-the-shelf components. Our system fully exploits the capability of the existing 72-channel AFTER chip designed for the T2K experiment and allows seamless migration to the 64-channel AGET chip, a pin-compatible evolution under production by the GET collaboration. The Feminos is a low complexity card designed to readout a FEC equipped with four AFTER chips (T2K model) or a newly assembled FEC populated with four AGET chips. The trigger clock module (TCM) is a synchronization board that allows system scaling up to 6912 channels with 24 Feminos and FECs, a commercial multi-port Gigabit Ethernet switch, and a data acquisition PC. We detail the design of the Feminos hardware, firmware and embedded software and explain how high performance, rapid development and low cost were reached. System operation and data acquisition throughput scaling with multiple Feminos are investigated. |
| Starting Page | 1 |
| Ending Page | 8 |
| File Size | 953747 |
| Page Count | 8 |
| File Format | |
| e-ISBN | 9781479905348 |
| DOI | 10.1109/NSSMIC.2013.6829739 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-10-27 |
| Publisher Place | South Korea |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Detectors Field programmable gate arrays Clocks Synchronization Silicon Noise Application specific integrated circuits |
| Content Type | Text |
| Resource Type | Article |
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