NDLI: A PET detector module using FPGA-only MVT digitizers

Content Provider	IEEE Xplore Digital Library
Author	Daoming Xi Chen Zeng Wei Liu Xiang Liu Lu Wan Heejong Kim Luyao Wang Chien-Min Kao Qingguo Xie
Copyright Year	2013
Description	Author affiliation: Dept. of Biomed. Eng., Huazhong Univ. of Sci. & Technol., Wuhan, China (Daoming Xi; Chen Zeng; Wei Liu; Xiang Liu; Lu Wan; Luyao Wang) \|\| Dept. of Radiol., Univ. of Chicago, Chicago, IL, USA (Heejong Kim; Chien-Min Kao) \|\| Wuhan Nat. Lab. for Optoelectron., Wuhan, China (Qingguo Xie)
Abstract	Multi-voltage threshold (MVT) is an amplitude-based sampling method. It takes timing samples when the event pulse crosses the user-defined thresholds. Only a few comparators and TDCs are required when implementing such digitizer. Previously, we have demonstrated an FPGA-only MVT digitizer based on this method. The FPGA-only MVT digitizer employs the differential I/Os in an FPGA as the required comparators and FPGA based TDCs. The implementation of this digitizer is entirely based on the FPGA. We have demonstrated that it is possible to implement a significant number of MVT digitizers by using a single FPGA. It is also flexible, as it allows us to readily modify, or add functions to, the implementation without requiring costly hardware changes. Currently, we are developing a PET detector module using the FPGA-only MVT digitizer. In this paper we describe the design and implementation of the detector module and report its performance properties. The detector module has a total detection sensitive area of 50mm × 50mm, an overall energy resolution of 15.1% FWHM at 511keV, and a module-level coincidence timing resolution of 684ps FWHM. In addition, our preliminary imaging with such detector module successfully resolves 1.6mm-diameter rods separated by 3.2mm.
Starting Page	1
Ending Page	5
File Size	297122
Page Count	5
File Format	PDF
e-ISBN	9781479905348
DOI	10.1109/NSSMIC.2013.6829063
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-27
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Detectors Positron emission tomography Energy resolution Crystals Timing Field programmable gate arrays PET FPGA LVDS MVT Digitizer all digital data acquisition (DAQ) system block detector
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in