NDLI: An efficient VLSI implementation of on-line recursive ICA processor for real-time multi-channel EEG signal separation

Content Provider	IEEE Xplore Digital Library
Author	Wei-Yeh Shih Jui-Chieh Liao Kuan-Ju Huang Wai-Chi Fang Cauwenberghs, G. Tzyy-Ping Jung
Copyright Year	2013
Description	Author affiliation: Swartz Center for Comput. Neurosci., Univ. of California San Diego, La Jolla, CA, USA (Jui-Chieh Liao; Kuan-Ju Huang; Cauwenberghs, G.; Tzyy-Ping Jung) \|\| Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan (Wei-Yeh Shih; Wai-Chi Fang)
Abstract	This paper presents an efficient VLSI implementation of on-line recursive ICA (ORICA) processor for real-time multi-channel EEG signal separation. The proposed design contains a system control unit, a whitening unit, a singular value decomposition unit, a floating matrix multiply unit and, and an ORICA weight training unit. Because the input sample rate of the ORICA processor is 128 Hz, the ORICA processor should produce independent components before the next sample is input in 1/128 s. Under the timing constraints of commutating multi-channel ORICA in real time, the design of the ORICA processor is a mixed architecture, which is designed as different hardware parallelism according to the complexity of processing units. The shared arithmetic processing unit and shared register can reduce hardware complexity and power consumption. The proposed design is implemented used TSMC 90nm CMOS technology with 8-channel EEG processing in 128 Hz sample rate of raw data and consumes 2.827 mW at 50 MHz clock rate. The performance of the proposed design is also shown to reach 0.0078125 s latency after each EEG sample time, and the average correlation coefficient between the original source signals and extracted ORICA signals for each 1s frame is 0.9763.
Starting Page	6808
Ending Page	6811
File Size	680770
Page Count	4
File Format	PDF
ISBN	9781457702167
ISSN	1557170X
DOI	10.1109/EMBC.2013.6611120
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-07-03
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electroencephalography Hardware Training Real-time systems Adders Vectors Process control
Content Type	Text
Resource Type	Article
Subject	Signal Processing Biomedical Engineering Health Informatics Computer Vision and Pattern Recognition

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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