NDLI: Stacking Technique of Known Good Rebuilt Wafers without Thru-Silicon Via Commercial Applications

Content Provider	IEEE Xplore Digital Library
Author	Val, C. Couderc, P. Boulay, N.
Copyright Year	2008
Description	Author affiliation: 3D Plus, Paris (Val, C.; Couderc, P.; Boulay, N.)
Abstract	A stacking technique of all types of bare dice has been developed. The various manufacturing steps as well as the main applications will be presented. From 2001 to 2005, an important European programme, WALPACK, funded up to 20 Miquest with St Microelectronics, CEA/LETI, Thales, and 3D Plus has allowed to establish the feasibility of a stacking technique totally wafer level process. A trademark registration :"Wirefree Die on Die (WDoD)" has been made for this process. The prototyping and pre series has been made thanks to an agreement between 3D Plus and Philips Semiconductors, now NXP. This wafer level process stacking technique has been named Wireless Die-on-Die (WDoD). It is based on the criteria which we used in the 1990 when we launched our mature and fully qualified 3-D technique: -Use of any kind of standard dice, which means non modified and multi-sourcing -Electrical tests of each level prior to stacking. -Stacking of the die with different size in order to build a System in Package The main steps are based on the following: .Pick-and-Place of the dice on a sticky membrane to make a Known Good Rebuilt Wafer "KGRW" .Moulding to insulate the edges of the dice and rigidify the rebuilt wafer .Redistribution layer (RDL) .Use of double adhesive tape to stack the different KGRW .Dicing of this stacking .Collective electroless plating of the edges of the dicing streets Direct laser patterning of the edges.
Starting Page	1306
Ending Page	1310
File Size	5118474
Page Count	5
File Format	PDF
ISBN	9781424421176
DOI	10.1109/EPTC.2008.4763611
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-09
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Stacking Packaging Wafer scale integration System testing Flash memory Communication industry Through-silicon vias Wire Wafer bonding Manufacturing
Content Type	Text
Resource Type	Article

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