NDLI: Advanced Metallization for 3D Integration

Content Provider	IEEE Xplore Digital Library
Author	Beica, R. Siblerud, P. Sharbono, C. Bernt, M.
Copyright Year	2008
Description	Author affiliation: Semitool, Inc., Kalispell, MT, USA (Beica, R.; Siblerud, P.; Sharbono, C.; Bernt, M.)
Abstract	Increasing demand for new and more advanced electronic products, with smaller form factor and superior functionality and performance, while reducing the cost, has driven the semiconductor industry to develop more innovative and emerging advanced packaging technologies. 3D packaging, using z-axis through silicon via (TSV) stacking concept has been and continues to be investigated by many of the semiconductor manufacturers and research institutes and is believed to be one of the most promising, if not the most promising concept that could successfully address the limitations of today's packaging technologies. There is a continuous increase of interest in development and study of applicability of this new chip stacking approach to existing and future devices; currently, more than fifty companies worldwide are involved in some sort of 3D TSV packaging developments. There are several steps involved in 3D chip stacking using TSV technology. Each of these steps requires different techniques, materials and processes, applications that have to be well understood and integrated in order to successfully be applied. This paper will address various electrodeposition processes applied to form 3D interconnects, from TSV deposition, which is the main metallization step that stays at the hearth of this new technology, to other metallization steps for additional connections, such as bumping and redistribution layers, already well known and applied processes in current wafer level packaging (WLP) applications. Advantages and difficulties associated with each of these technologies, with more focus on 3D vertical integration using TSV copper interconnect, including the approaches taken to overcome them, will be presented. Deposition conditions for bumping were optimized in order to enable higher deposition rates. For other through- mask applications, such as redistribution lines (RDL), the complexity of the pattern, deposition rate, chemical formulation and process parameters were found to have a significant effect on within-die (WID) thickness distribution. In case of WLP structures of thick metal and high aspect ratios, seed layer uniformity proved to be essential for achieving void-free deposition. Void-free structures, especially for high aspect ratio vias seeded with dry methods, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), seem difficult to obtain. New approaches, such as seed layer repair (SLE) or direct on barrier electrodeposition (DOB) can provide superior uniformity and coverage of the conductive layer, necessary for a uniform nucleation of copper electrodeposition process along the entire sidewall of the via, at significantly lower costs. This paper will present TSV structures obtained with wet chemical processes applications for both seed layer and via filling. Besides seed layer uniformity, additional factors were identified to also be critical for successfully filling deep vias. They are: via profile, wettability of vias, superior performance of chemistries and high performance equipment. By selecting the most appropriate deposition methods and optimizing the chemical formulations together with the process parameters, void-free TSV structures can be obtained.
Starting Page	212
Ending Page	218
File Size	8163148
Page Count	7
File Format	PDF
ISBN	9781424421176
DOI	10.1109/EPTC.2008.4763436
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-09
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Metallization Through-silicon vias Chemical vapor deposition Semiconductor device packaging Stacking Chemical processes Electronics packaging Copper Filling Industrial electronics
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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