NDLI: Chip In Wafer for Integrated System

Content Provider	IEEE Xplore Digital Library
Author	Souriau, J.-C. Faivre, M.-E. Sillon, N.
Copyright Year	2008
Description	Author affiliation: CEA-LETI Minatec, Grenoble, France (Souriau, J.-C.; Faivre, M.-E.; Sillon, N.)
Abstract	System integration is clearly a driving force for innovation in packaging. The need for miniaturization has led to new system in package (SiP) architectures, which combine a whole range of different technologies. However, cost is the critical issue in SiP packaging as individual operations are currently necessary to complete each individual package. Taking into account all the developments that have been made to date on wafer level packaging, it has been proposed to establish SiP at wafer level. The process presented in this paper proposes to use silicon wafer as frame. Known Good Dies are fitted into through cavities and sealed with polymer. This process enables coplanar chip active face with the host silicon wafer. Due to the consistency given by the silicon frame, the wafer can be treated in wafer line for the above IC process such as passive integration, via plating and pad redistribution, bumping, testing and dicing. The paper describes technologies developed for chip integration in silicon wafer (CIW) and first results on wafer characterization will be set out.
Starting Page	999
Ending Page	1004
File Size	4523291
Page Count	6
File Format	PDF
ISBN	9781424421176
DOI	10.1109/EPTC.2008.4763560
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-09
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon Polymers Packaging Wafer scale integration Costs Optical sensors Curing Vehicles Integrated circuit testing Paper technology
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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