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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Meyer, T. Ofner, G. Bradl, S. Brunnbauer, M. Hagen, R. |
| Copyright Year | 2008 |
| Description | Author affiliation: Infineon AG, Regensburg (Meyer, T.; Ofner, G.; Bradl, S.; Brunnbauer, M.; Hagen, R.) |
| Abstract | Wafer Level Packaging (fan-in WLB, Wafer Level Ball Grid Array) is the upcoming future packaging technology with many advantages in comparison to standard Ball Grid Array Packages. Advantages are especially the small package dimensions, excellent electrical and thermal performance, highest package interconnect density and integration possibilities at lowest packaging cost. Today, standard (fan-in) WLBs are the technology of choice mainly for small to medium sized chips with a moderate number of interconnects. The reason for the limited number of interconnects is the need to fit all interconnects on the die in a given terminal pitch. Since this is not generally possible, Infineon has developed a fan-out WLB Technology, called embedded Wafer Level Ball Grid Array (eWLB). The technology is based on a reconstituted wafer which is built prior to the thin-film technology, adding space around the dies to increase the possible number of interconnects on the package. This Reconstituted Wafer is afterwards processed by applying dielectric, redistribution, solder stop and balls in a modified thin-film and backend technology. The new wafer level package concept complies with the directives for environmental friendly technologies like WEEE and RoHS. eWLB passed all performed Standard JEDEC reliability tests without optical or electrical fails on a test vehicle basis. We will introduce recent results of the platform development of the eWLB technology and show the capabilities of Infineon's molded embedded Wafer Level Package for future system integration. |
| Starting Page | 994 |
| Ending Page | 998 |
| File Size | 5780927 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424421176 |
| DOI | 10.1109/EPTC.2008.4763559 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-12-09 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Electronics packaging Wafer scale integration Semiconductor device packaging Space technology Integrated circuit packaging Dielectric thin films Testing Costs Assembly Semiconductor thin films |
| Content Type | Text |
| Resource Type | Article |
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