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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kyung-Wook Paik Ho-Young Son Il Kim Chang-Kyu Chung |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Mater. Sci. & Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea (Kyung-Wook Paik; Ho-Young Son; Il Kim; Chang-Kyu Chung) |
| Abstract | Recently, wafer level package (WLP) has become one of the promising packaging technologies due to its advantages such as fewer processing steps, lower cost, and enhanced device performance compared to single chip packages. Many developments on new WLP design, materials and processes have been accomplished according to the electrical, mechanical performance and reliability requirement of the devices to be packaged. For lower cost, higher performance and environmentally green packaging process, anisotropic conductive adhesives(ACAs) including films (ACFs) and pastes (ACPs) assembly has been widely used such as ultra-fine pitch flat panel display (FPD) and general semiconductor packaging applications. However, there has been no previous attempt using ACAs on WLP. In this study, wafer level packages using pre-applied ACAs on an entire wafer for flip-chip assembly on organic substrates have been investigated, and the effect of process parameters, such as ACAs lamination/coating, wafer dicing, and ACAs flip chip assembly, on the ACA wafer level package performance were investigated. After ACA lamination or coating on Au stud bumped 6 inch wafers, and subsequent singulation by diamond sawing. And then singulated chips were flip-chip assembled on an organic substrate using a thermo-compression bonding method. ACA joints between Au stud bumps and substrate metal pads using WLACA method showed stable bump contact resistance of 8~9m¿ per a bump which is the same as the typical thermocompression-bonded ACA joint. Reliability of the ACA-WLP joints are the same as that of thermocompression-bonded ACA joint. |
| Starting Page | 450 |
| Ending Page | 456 |
| File Size | 7654078 |
| Page Count | 7 |
| File Format | |
| ISBN | 9781424421176 |
| DOI | 10.1109/EPTC.2008.4763475 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-12-09 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Electronics packaging Wafer scale integration Semiconductor device packaging Assembly Substrates Costs Lamination Coatings Gold Process design |
| Content Type | Text |
| Resource Type | Article |
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