NDLI: Study on Board Level Drop Reliability of Wafer Level Chip Scale Package with Leadfree Solder

Content Provider	IEEE Xplore Digital Library
Author	Zhang Xueren Zhu Wenhui Edith, P. Tan Hien Boon
Copyright Year	2008
Description	Author affiliation: Packaging Anal. & Design Center, United Test & Assembly Center, Ltd., Singapore (Zhang Xueren; Zhu Wenhui; Edith, P.; Tan Hien Boon)
Abstract	Wafer level chip scale package (WLCSP) is a promising packaging technology to accommodate the demand for small, portable handheld electronic. This bare-die bumped package is able to offer significant area savings, improve package electrical parasitics and power dissipation performance over substrate-based BGA packages. However, its board level reliability especially mechanical performance under shock impact is a great concern for handheld electronics. In this paper, daisy chained WLCSP packages with leadfree solder bumps have been assembled on customer boards, and board level drop test has been carried out on a JEDEC compatible drop tester. First failure is found at 42 drops among 36 samples. All the electrical failure found is caused by the breakage of Cu trace under critical corner ball at PCB side. To understand the failure mechanism and built up the life prediction model for WLCSP, finite element simulation has been carried out by explicit dynamic software ANSYS/LS-Dyna. Strain-rate dependent elastoplastic model for solder is developed vi nano-indentation test and implemented to the simulation. highest interface peeling stress is found at one of the corner and between solder and PCB Cu pad, which is exactly correlated with failure location from the test results. This failure mode is different from those results for WLCSP open publications, where failure mostly happened at component side. From simulation analysis, it is understood that the maximum stress located at PCB side is mainly due to the Cu trace connected to the Cu pad along board length direction. Recommendation on Cu trace alignment has been proposed to improve PCB design accordingly. Bump structure effect has also been simulated, and it is shown that RDL design with soft dielectric passivation layer is very helpful for the drop reliability performance improvement of WLCSP.
Starting Page	1096
Ending Page	1101
File Size	5837738
Page Count	6
File Format	PDF
ISBN	9781424421176
DOI	10.1109/EPTC.2008.4763575
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-09
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Chip scale packaging Wafer scale integration Lead Electronics packaging Testing Predictive models Stress Power dissipation Electric shock Assembly
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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