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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Mengzhi Pang Kaufmann, M. Sze, H. Sharifi, R. Tan, K. Neo, C.W. Ramakrishna, R. Karikalan, S. Khan, R. |
| Copyright Year | 2012 |
| Description | Author affiliation: Broadcom Corporation, 3151 Zanker Road, San Jose, CA 95134 (Mengzhi Pang; Kaufmann, M.) || Broadcom Corporation, 5300 California Avenue, Irvine, CA 92617 (Sze, H.; Sharifi, R.; Karikalan, S.) || Broadcom Corporation, 500 N. Juniper Dr, Chandler, AZ, 85226 (Ramakrishna, R.; Khan, R.) || Broadcom Corporation, 29 Woodlands Industrial Park, Singapore, 757716 (Tan, K.; Neo, C.W.) |
| Abstract | Significant challenges are encountered to enable large-die fine-pitch lead-free-bump flip chip devices, especially with extreme low-k (ELK) silicon technology for 40 nm and beyond. Such failures are often observed as die ELK stack-up fractures, lead-free bump cracking, underfill delamination, high warpage-induced BGA reliability issues, etc. The underlying root cause can be attributed to elevated thermo-mechanical stress within the packaging when lead-free bump material is used for the die-to-packaging interconnect. This paper presents an innovative approach to addressing these technical problems by applying mechanically compliant lead-free bump metallurgy. In conjunction with several other aspects of assembly and packaging material optimization, this solution is capable of delivering 100% lead-free flipchip packaging with a die size of up to 20×20 mm and a package size of up to 52.5×52.5 mm per side. |
| Starting Page | 597 |
| Ending Page | 602 |
| File Size | 1302991 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467319669 |
| ISSN | 05695503 |
| e-ISBN | 9781467319652 |
| e-ISBN | 9781467319645 |
| DOI | 10.1109/ECTC.2012.6248891 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-05-29 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Soldering Substrates Lead Packaging Stress Tin |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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