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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yong Liu Qiuxiao Qian Shichun Qu Martin, S. Jeon, O. |
| Copyright Year | 2012 |
| Description | Author affiliation: Fairchild Semiconductor Corp, 82 Running Hill Road, Mail Stop 35-2E, South Portland, ME 04106 (Yong Liu; Qiuxiao Qian; Shichun Qu; Martin, S.; Jeon, O.) |
| Abstract | Intensive FEA modeling was applied to the investigation of early solder joint failures of WLCSP mounted on test PCBs. In particular, stress in assembly reflow process was studied with 25 balls; 0.4 mm pitch WLCSP and PCBs with specially placed plated though vias. The 25 ball WLCSP in the study has 5×5 ball array, which corresponds to 16 outmost solder joints and nine inner solder joints, all soldered to the matching copper pads on the test PCB. Three PCB designs were modeled to understand the impact of PCB through via arrangement on stresses in solder joints during assembly reflow process: design #1 has no PCB through vias at all; design #2 has plated through vias under nine inner PCB copper pads; design #3 has plated through vias under all 25 PCB copper pads. The modeling results disclose that PCB design #2 with plated through vias under nine inner PCB copper pads induces the highest solder stress in all three models. Contrary to common sense of higher stress on corner solder joints due to coefficient of thermal expansion (CTE) mismatch of silicon and PCB, the maximum stresses of design #2 actually occur on the inner solder joints. The simulation results match well with experimental observations. For PCB design #1 and #3, highest solder stress is lower than stress in design #2. In addition, in both cases, the maximum stress locates on the corner solder joints. New PCB design guidelines have since been implemented based on the simulation. Due to the improvement of the design, premature solder joint failure has not been recorded. |
| Starting Page | 959 |
| Ending Page | 964 |
| File Size | 1215810 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467319669 |
| ISSN | 05695503 |
| e-ISBN | 9781467319652 |
| e-ISBN | 9781467319645 |
| DOI | 10.1109/ECTC.2012.6248952 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-05-29 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Soldering Stress Copper Semiconductor device modeling Joints Arrays Materials |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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