NDLI: Optimization of the Thermomechanical Reliability of a 65 nm Cu/Low-<formula formulatype=inline><tex Notation=TeX>$k$</tex></formula> Large-Die Flip Chip Package

Content Provider	IEEE Xplore Digital Library
Author	Ong, J.M.G. Tay, A.A.O. Zhang, X. Kripesh, V. Lim, Y.K. Yeo, D. Chan, K.C. Tan, J.B. Hsia, L.C. Sohn, D.K.
Copyright Year	1999
Abstract	The trend toward finer pitch and higher performance integrated circuit devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermomechanical failure is one of the major bottlenecks in the development of Cu/low-k larger-die flip chip packages. This paper describes the optimization of the structural design of Chartered's C65 nm 21 mm times 21 mm die size flip-chip ball grid array package incorporated with fully active and functional ninemetal Cu/low-k layers and 150 mum interconnect pitch. The lowk material used in this paper is nonporous SiCOH with a k value of 2.9. A parametric study using 2-D plane strain finite element analysis was performed to study the effect of various parameters on the reliability of the large-die package in order to arrive at an optimized design. In order to have a simple criterion to predict the reliability of the yet-to-be-built largedie package, reliability tests were carried out on some existing 15 mm times 15 mm die CvJlow-k flip chip packages which were identical to the 21mm times 21mm die package except for the size. The packages were found to pass the reliability tests. 2-D plane strain finite element analyses were then performed on the 15 mm times 15 mm die. The computed delamination stresses at the low-k layer and the strain energy density dissipation per cycle in the critical solder (DeltaW) were then used as a benchmark for the design of a larger flip chip package. The efficacy of the polymer encapsulated dicing lane technology was established. In this paper, the effect of the number of fluorosilicate glass layers, die thickness, substrate thickness, Cu post height, and underfill type on the delamination stresses in the low-k layer and DeltaW were determined. Specimens of the optimized large-die package were then fabricated and subjected to reliability tests. They were all found to pass the reliability tests. From these reliability tests, new benchmark values of the delamination stresses at the low-k layer and DeltaW are obtained, which can be used to aid in the design of large-die Cu/low-k flip chip packages.
Sponsorship	IEEE Components, Packaging, and Manufacturing Technology Society
Starting Page	838
Ending Page	848
Page Count	11
File Size	1320036
File Format	PDF
ISSN	15213331
Volume Number	32
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Thermomechanical processes Packaging Testing Copper Flip chip Dielectric materials Capacitive sensors Delamination Stress Design optimization solder joint reliability 65 nm Cu/low-$k$ finite element analysis flip chip package large-die
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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