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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kurashina, M. Mizutani, D. Koide, M. Watanabe, M. Fukuzono, K. Suzuki, H. |
| Copyright Year | 2012 |
| Description | Author affiliation: Fujitsu Interconnect Technologies, Ltd., 36, Kitaowaribe, Ooaza, Nagano 381-8501, Japan (Suzuki, H.) || Fujitsu Advanced Technology, Ltd., 1-1, Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan (Koide, M.; Watanabe, M.; Fukuzono, K.) || Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi-shi Kanagawa 243-0197, Japan (Kurashina, M.; Mizutani, D.) |
| Abstract | Due to inadequate rigidity, warpage of coreless substrates is generally large compared to other types of LSI package substrates. Therefore, the most important problem in the application of coreless substrates is warpage reduction during the reflow process. So far, there have been only a limited number of reports on coreless substrates for large-size LSI packages. Moreover, there have been very few examples that discussed substrate layer structure designs for warpage reduction and reliability improvement in the LSI assembly process. In the present study, we focus on developing coreless packages for large-size LSIs. To achieve our goal, we adopted the following development processes. First, we designed analytical models with different layer structures comprising two kinds of materials, and investigated the effect of layer structure on warpage reduction using warpage simulations. Next, we made four kinds of real coreless substrates with layer structures identical to the simulation models, and verified the actual thermal warpage behavior. Finally, we investigated the thermal stress reliabilities of these substrates after LSI mounting. From the results, we found that warpage reduction and reliability enhancement of coreless substrates were realized by arranging the high rigidity materials on the external layers of the substrates. |
| Starting Page | 1378 |
| Ending Page | 1383 |
| File Size | 797199 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467319669 |
| ISSN | 05695503 |
| e-ISBN | 9781467319652 |
| e-ISBN | 9781467319645 |
| DOI | 10.1109/ECTC.2012.6249015 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-05-29 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Substrates Large scale integration Temperature measurement Reliability Resins Solid modeling |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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