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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sakuma, K. Smith, K. Tunga, K. Perfecto, E. Wassick, T. Pompeo, F. Nah, J. |
| Copyright Year | 2012 |
| Description | Author affiliation: IBM Microelectronics Division, 2070 Route 52, Hopewell Junction, NY, 12533, U.S.A. (Sakuma, K.; Smith, K.; Tunga, K.; Perfecto, E.; Wassick, T.; Pompeo, F.) || IBM T. J. Watson Research Center, 1101 Kitchawan Road, Yorktown, NY, 10598, U.S.A. (Nah, J.) |
| Abstract | A differential heating/cooling chip join method was developed for Pb-free flip chip packaging of ultra low-k (ULK) technology Si chips on organic substrates to prevent Chip-Package Interaction (CPI) — related damage upon chip joining. A chip was mounted to a bonder head and a substrate was located on a base plate and they were held at different elevated temperatures during the bonding process. The temperature difference between the Si chip and the organic substrate during assembly provides a substantially matched thermal expansion and minimizes stress induced by coefficient of thermal expansion (CTE) mismatch. From the modeling study, it was confirmed that chip warpage, Controlled Collapse Chip Connection (C4) stresses/strains, and ULK stresses decreased significantly by differential heating/cooling chip join method, with further improvement noted as the substrate temperature was decreased during the bonding process. X-ray, scanning electron microscope (SEM) and C-mode scanning acoustic microscope (C-SAM) were used to examine the defects after flip chip assembly. Noncontact white light reflectometry was also used to measure the warpage shape of the assembled silicon chip and the organic substrate. Observation under C-SAM indicated that fractures in the ULK layers were dramatically reduced by the differential heating/cooling chip joining process compared to the conventional reflow process. Non-destructive X-ray images indicated there were no solder bridging in any area of the chip interconnects. The experimental results showed that the differential heating/cooling chip join process can effectively reduce fractures in the ULK layers and prevent C4 bump bridging in a large die package with low-K dielectric constant device integration and high Ag content solder bumps. |
| Starting Page | 430 |
| Ending Page | 435 |
| File Size | 905592 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467319669 |
| ISSN | 05695503 |
| e-ISBN | 9781467319652 |
| e-ISBN | 9781467319645 |
| DOI | 10.1109/ECTC.2012.6248866 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-05-29 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Cooling Heating Substrates Stress Silicon Laminates Semiconductor device modeling |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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