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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Lannon, J. Hilton, A. Huffman, A. Lueck, M. Vick, E. Goodwin, S. Cunningham, G. Malta, D. Gregory, C. Temple, D. |
| Copyright Year | 2012 |
| Description | Author affiliation: RTI International, Research Triangle Park, NC (Lannon, J.; Hilton, A.; Huffman, A.; Lueck, M.; Vick, E.; Goodwin, S.; Cunningham, G.; Malta, D.; Gregory, C.; Temple, D.) |
| Abstract | Two 3D Si interposer demonstration vehicles containing through-Si vias (TSVs) were successfully fabricated using integration of two different TSV formation and multilevel metallization (MLM) process modules. The first Si interposer vehicles were made with a dual damascene frontside MLM (5 levels), backside TSV (unfilled, vias-last), and backside metallization (2 levels) process sequence on standard thickness 6” wafers. The front-side MLM was comprised of 4 metal routing layers (2 μm Cu with 2 μm oxide interlayer dielectric) and 1 metal pad layer. Electrical yield as high as 100% was obtained on contact chain test structures containing 26,400 vias between the front-side MLM layers, while the average contact resistance between the dual damascene levels was < 4 MΩ per via. TSV dimensions of 100 and 80 μm diameter and 6:1 aspect ratio were investigated. DRIE bottom clear process conditions were optimized for each via dimension to produce 100% yield on TSV contact chains with up to 540 vias. The optimized DRIE conditions also resulted in TSV resistance below 30 MΩ and sufficient TSV isolation resistance (>100MΩ/via at 3.3V) for the target application. Functional testing of two die (4 cm × 3.7 cm die size) showed that 99% of the functional circuit path nets had acceptable continuity and isolation. The second Si interposer vehicles were fabricated using a vias-first TSV (filled, blind vias), wafer-level packaging (WLP) front-side MLM (2 levels), wafer thinning (via reveal), and WLP-MLM (1 level) process sequence on stock 6” wafers. Via dimensions for the viasfirst interposers were 50 μm diameter × 315 μm depth or 80 μm diameter × 315 μm depth (6:1 or 4:1 aspect ratios). The front and backside MLM was formed with a 2 μm Cu routing layer and one of two spin-on dielectrics (polyimide or ALX) for evaluation of polymer dielectric process compatibility with Cu-filled TSVs and thinned wafer processing. Details of the process modules and process integration required to realize the TSV Si interposers are described. |
| Starting Page | 268 |
| Ending Page | 273 |
| File Size | 880061 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467319669 |
| ISSN | 05695503 |
| e-ISBN | 9781467319652 |
| e-ISBN | 9781467319645 |
| DOI | 10.1109/ECTC.2012.6248839 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-05-29 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Through-silicon vias Silicon Vehicles Metallization Routing Passivation |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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