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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ishibashi, K. |
| Copyright Year | 2007 |
| Description | Author affiliation: Nokia Japan Co. Ltd., Tokyo (Ishibashi, K.) |
| Abstract | BGA package warpage during reflow soldering can cause open solder joint failure and in PoP case it's more critical to top joint (package-package interface) than to bottom joint (package-motherboard interface), as far as the former uses conventional flux dipping for SMT and the latter uses paste-printing. Design guideline for PoP reflow warpage was proposed based on the discussion of solder joint collapse at reflow. In order to avoid stacking failure of top joint, package reflow warpage defined on whole substrate should be less than 72 mum for 0.65 mm top pitch and 66 mum for 0.5 mm top pitch over solder liquidus temperature. Monte Carlo simulation study shows PoP stacking yield is sensitive to dimensional variations of package reflow warpage and bottom package top-pad size, and small change in those dimensions can create large stacking yield loss. |
| Starting Page | 1403 |
| Ending Page | 1408 |
| File Size | 4745987 |
| Page Count | 6 |
| File Format | |
| ISBN | 1424409845 |
| ISSN | 05695503 |
| DOI | 10.1109/ECTC.2007.373978 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-05-29 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Packaging Stacking Surface-mount technology Assembly Cellular phones Manufacturing Poles and towers Reflow soldering Guidelines Temperature sensors |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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