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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sakuma, K. Andry, P.S. Dang, B. Maria, J. Tsang, C.K. Patel, C. Wright, S.L. Webb, B. Sprogis, E. Kang, S.K. Polastre, R. Horton, R. Knickerbocker, J.U. |
| Copyright Year | 2007 |
| Description | Author affiliation: IBM T. J. Watson Res. Center, Yorktown Heights (Sakuma, K.; Andry, P.S.; Dang, B.) |
| Abstract | In this paper a three-dimensional (3D) chip stacking technology using fine-pitched interconnects with lead-free solder is described. Different interconnect metallurgies such as Cu/Ni/In, Cu/In and Cu/Sn were considered and the bonding conditions to optimize the bonding parameters were determined. The effect of intermetallic compound (IMC) formation on the mechanical properties of the joins is discussed. Unlike standard 100-micron C4 solder balls, very small solder volumes (< 6 microns high) were investigated. The mechanical properties were evaluated by shear and impact shock testing, while scanning electron microscopy (SEM) and optical microscopy were used to study the morphology of the IMC layers in solder joins before and after annealing. It was found that Cu/Ni/In and Cu/In interconnections have slightly lower shear strength per bump. While these values were lower than the Cu/Sn joins, the Cu/Ni/In chips passed the impact shock test for a simulated heat sink mass of 27 $g/cm^{2}.$ The reasons for the differences in reliability of these metallurgies are discussed. 3D chip stacking using two-layers of chips with fine-pitch lead-free interconnects was demonstrated. The resistance of link chains comprising through-vias, lead-free interconnects and Cu links were measured using a 4-point probing method. The average resistance of the through-via including the lead-free interconnect was 21 mOmega. |
| Starting Page | 627 |
| Ending Page | 632 |
| File Size | 6338484 |
| Page Count | 6 |
| File Format | |
| ISBN | 1424409845 |
| ISSN | 05695503 |
| DOI | 10.1109/ECTC.2007.373862 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-05-29 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Stacking Environmentally friendly manufacturing techniques Lead Optical microscopy Scanning electron microscopy Tin Bonding Mechanical factors Electric shock Testing |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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