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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zhai, C.J. Too, S.S. Master, R.N. |
| Copyright Year | 2007 |
| Description | Author affiliation: Adv. Micro Devices, Inc., Sunnyvale (Zhai, C.J.; Too, S.S.; Master, R.N.) |
| Abstract | Lid or heat spreader in flip chip packages has become a vital component for high performance and high power IC applications. While mechanics and reliability of flip chip packages have been extensively investigated in the last decade, majority of the research was focused on the packages without lid. Hence, we still lack of fundamental understanding of the impact of lid on the package reliability. In this paper we systematically investigated the interaction between the lid and the organic flip chip package via 3D FEA and 2D fracture analysis. The main reliability concerns that we tried to address included die and package warpage, underfill delamination and chip-package-interaction during lid attachment process as well as temperature cycling test. The primary design and process parameters are the lid adhesive properties and the relative die size to the lid cavity size. We found that there existed a worst-case die size to lid cavity size ratio which imposed the greatest risk to the package reliability. As a result, larger dies do not necessarily result in worse reliability. The simulation also suggested that die size plays a more important role in the reliability of flip chip packages with lid, comparing to those without lid. Warpage measurement was carried out via laser-based surface profiling on various die sizes to validate the model. |
| Starting Page | 1091 |
| Ending Page | 1096 |
| File Size | 3917466 |
| Page Count | 6 |
| File Format | |
| ISBN | 1424409845 |
| ISSN | 05695503 |
| DOI | 10.1109/ECTC.2007.373933 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-05-29 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Flip chip Power system reliability Integrated circuit packaging Power integrated circuits Delamination Temperature Testing Process design Semiconductor device measurement Size measurement |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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