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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Schaper, L. Burkett, S. Gordon, M. Cai, L. Liu, Y. Jampana, G. Abhulimen, I.U. |
| Copyright Year | 2007 |
| Description | Author affiliation: Univ. of Arkansas, Fayetteville (Schaper, L.; Burkett, S.) |
| Abstract | A great deal of work has been done in creating 3-D VLSI by wafer stacking and through silicon via (TSV) processing for dense Z-axis interconnects. Various methods for wafer attachment have been used, including polymer glue, oxide-oxide bonding, and direct metallic bonding. Yet these wafer attachment methods may not be the best way to assemble 3-D systems from VLSI elements. Systems consist of more than silicon ICs. Many systems, particularly those designed for RF or sensor applications, may need to assemble both III-V and silicon layers with TSVs, remove significant amounts of heat, provide integrated decoupling and power distribution, and avoid cumulative yield issues by pretesting individual die layers before assembly. Typically, each layer may be a miniature subsystem, so that Z-axis interconnect demand can be satisfied by connections on 100 -200 mum pitch. This paper describes an advanced 3-D packaging concept using die stacking rather than wafer bonding. To deal with the CTE mismatch of different materials, compliant copper posts are used to join individual layers. The copper is also used to form a fluid dam around the resulting channel between each pair of die. Circulating fluid is pumped through these channels for heat removal. Sequential attachment of pretested layers is accomplished by forming copper/tin intermetallics. Decoupling and power distribution are provided by thin film capacitors between copper distribution planes on dedicated silicon layers. The results of process development on the various aspects of this approach will be presented. TSVs of 20 mum diameter on 100 mum pitch have been fabricated in wafers thinned to 100 mum thick. Copper posts 30 mum in diameter and 80 mum high have been demonstrated. The results of tests on via and post daisy chains will be presented. Decoupling layers based on thin-film $Ta_{2}O_{5}$ dielectric capacitors will be described. The design of a complete test vehicle intended to demonstrate the integration of these methods will be presented. This novel concept for packaging miniature 3-D VLSI systems appears well-suited to high power RF and other system applications. |
| Starting Page | 853 |
| Ending Page | 857 |
| File Size | 5220996 |
| Page Count | 5 |
| File Format | |
| ISBN | 1424409845 |
| ISSN | 05695503 |
| DOI | 10.1109/ECTC.2007.373898 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-05-29 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Very large scale integration Copper Silicon Wafer bonding Assembly systems Stacking Radio frequency Power distribution Packaging Capacitors |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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