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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chang, H.H. Shih, Y.C. Hsiao, Z.C. Chiang, C.W. Chen, Y.H. Chiang, K.N. |
| Copyright Year | 2009 |
| Description | Author affiliation: Department of Power Mechanical Engineering, National Tsing Hua University, 101, Section 2, Kuang-Fu Road, Hsinchu, Taiwan 30013, R.O.C. (Chiang, K.N.) || Industrial Technology Research Institute, Bldg. 17, 195, Sec. 4, Chung Hsing Rd. Chutung, Hsinchu, Taiwan, R.O.C. (Chang, H.H.; Shih, Y.C.; Hsiao, Z.C.; Chiang, C.W.; Chen, Y.H.) |
| Abstract | In this study, bottom-up electroplating is used for TSV (Through Silicon via) fabrication. With the metal temporarily bonding technology, we could remove the handling substrate and perform the chip stacking process. The TSVs made by bottom-up electroplating do not need the expensive MOCVD seed layer deposition and special designed electroplater/solution. Moreover, it is independent with the DRIE angle and the scallop at the sidewall of the vias. By using the bottom-up electroplating technology, we could fabricate the TSVs in much shorter process time to save the process cost. From the X-Ray images and the SEM pictures, the diameter of the vias is 5.3 micron meters and the length of the vias is 67 micron meters. The aspect ratio of the bottom-up electroplated TSVs is larger than 12 and all the vias are definitely void free. X-Ray image also shows the process yield is very high. After the thermal shock reliability test, the resistance measurement and the vias are fine from the SEM pictures. There is no crack found at the sidewall of the vias. After the TSV process, the bonded electrode continues to serve as electrode for the mask-less Sn electroplating. The electroplating current goes through the bottom electrode TSVs and the Sn is electroplated on the TSVs without mask define. Sn bump served as mechanical and electrical connection. We also demonstrate the dry etching process for wafer thinning on a 170°C thermal release tape with handling substrate. After the etching process, the thickness of the chip is about 5µm and then it is released from the handling substrate successfully. For thin wafer handling technology, we proposed a metal temporarily bonding technology. Au to Au bonding is used here for metal temporarily bonding. After the wafer thinning process, the sample could sustain high temperature process without crack and could be removed from the handling substrate after the process. This study also demonstrates the process flow for the 3D chip stacking by using the bottom-up electroplated TSVs. The handling substrate is removed by metal temporarily bonding technology and the interconnection is done by Cu/Sn bump. Based on this technology, the TSVs in the 3D chip stacking could be made in shorter electroplating time and low cost way by a traditional electroplater. |
| Starting Page | 1177 |
| Ending Page | 1184 |
| File Size | 2123998 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781424444755 |
| ISSN | 05695503 |
| DOI | 10.1109/ECTC.2009.5074161 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-05-26 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Wafer bonding Tin Stacking Electrodes Through-silicon vias Costs X-ray imaging Gold Silicon Fabrication |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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