NDLI: High-performance engineered gate transistor-based compact digital circuits

Content Provider	IET Digital Library
Author	Kumar, S. Loan, S. A. Alamoud, A. M.
Abstract	A novel method for designing and realising compact digital circuits by engineering MOSFET gate electrode is proposed. The novelty is the use of gate engineered single devices in the pull-up (PU) and pull-down (PD) paths of a static CMOS gate instead of multiple transistors as used in conventional CMOS implementations of circuits. Herein, two input NAND, NOR, and exclusive-OR (XOR) gates employing the proposed gate engineering concept are designed and simulated. Engineered gate N-type MOS and P-type MOS are used for PD and pull-up circuits, respectively. Since only two devices are used for a complete circuit: one in PU network and other in PD network; therefore, area and power of the proposed circuits get reduced significantly in comparison with the conventional static CMOS circuits. Mixed mode simulations have shown that the proposed technique realises NAND, NOR and XOR operations perfectly and it can be extended to realise other combinational and sequential circuits easily.
Starting Page	138
Ending Page	140
Page Count	3
ISSN	00135194
Volume Number	53
e-ISSN	1350911X
Issue Number	Issue 3, Feb (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/53/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2016.3899
Journal	Electronics Letters
Publisher Date	2016-12-16
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	CMOS Integrated Circuit CMOS Logic Circuit Combinational Circuit Design And Testing Electrode Engineered Gate N-type MOS Engineered Gate P-type MOS Engineered Gate Transistor-based Compact Digital Circuit Engineering MOSFET Gate Electrode Equivalent Circuit Exclusive-OR Gate Gate Engineered Single Device Insulated Gate Field Effect Transistors Integrated Circuit Design Layout Logic Circuit Logic Gate Mixed Mode Simulation Modelling And Testing MOSFET NAND Circuit NAND Gate NOR Circuit NOR Gate PD Path PU Path Pull-up Path Pulldown Path Semiconductor Device Modelling Semiconductor Integrated Circuit Design Sequential Circuit Static CMOS Gate Circuit XOR Gate
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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