NDLI: An area efficient surviving paths unit for the Viterbi algorithm

Content Provider	IEEE Xplore Digital Library
Author	Dabiri, D. Blake, I.F.
Copyright Year	1999
Description	Author affiliation: LSI Logic Corp., Milpitas, CA, USA (Dabiri, D.)
Abstract	A new surviving paths unit (SPU) is described wherein the decision bits produced in the add-compare-select unit (ACSU) of a parallel architecture for the Viterbi algorithm are prepared for efficient storage in a single compact random access memory (RAM). A significant reduction in the size of the RAM is achieved by pre-processing the data in an especially designed unit. The new SPU never requires a memory bandwidth more than the least possible bandwidth imposed by the throughput of the ACSU. A novel interface unit, hereafter referred to as the ACS interface unit (ACSIU), resolves surviving paths down to a pre-determined depth on the trellis diagram of a finite state Markov chain, and breaks the decision bits into a sequence of successive vectors, each of the same size as the word-size of the RAM. At any trace-back step, a subset of the previous content of the trace-back register is used to generate the address for the current output of the RAM. A disjoint subset of the current content of the trace-back register is used to select a pre-determined number of bits from the output of the RAM. The selected bits are used to update the content of the trace-back register. The trace-back register after a sufficient number of trace-back steps, contains the estimated bits.
Starting Page	300
Ending Page	304
File Size	440396
Page Count	5
File Format	PDF
ISBN	078035284X
DOI	10.1109/ICC.1999.767949
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-06-06
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Viterbi algorithm Read-write memory Maximum likelihood decoding Bandwidth Random access memory Throughput Large scale integration Logic Maximum likelihood estimation Convolutional codes
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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