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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zhu, Hongbo Shibata, Tadashi |
| Copyright Year | 2012 |
| Description | Author affiliation: Dept. of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan (Shibata, Tadashi) || VLSI Design and Education Center (VDEC), The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan (Zhu, Hongbo) |
| Abstract | A VLSI image processor capable of extracting motion features from moving images in real time has been developed employing row-parallel and pixel-parallel architectures based on the digital pixel sensor (DPS) technology. Directional edge filtering of input images is carried out in row-parallel processing to minimize the chip real estate. To achieve a real-time response of the system, a fully pixel-parallel architecture has been explored in adaptive binarization of filtered images for essential feature extraction as well as in their temporal integration and derivative operations. As a result, self-speed-adaptive motion-feature-extraction has been established. The chip was designed and fabricated in a 65-nm CMOS technology and used to build an object detection system. Motion-sensitive target image localization was demonstrated as an illustrative example. |
| Starting Page | 1612 |
| Ending Page | 1615 |
| File Size | 2165490 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467302180 |
| ISSN | 02714302 |
| e-ISBN | 9781467302197 |
| DOI | 10.1109/ISCAS.2012.6271563 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-05-20 |
| Publisher Place | Korea (South) |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Image edge detection Feature extraction Arrays Adders Very large scale integration Sorting Random access memory |
| Content Type | Text |
| Resource Type | Article |
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