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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Xinjian Zheng Yiwei Zhang Bo Peng |
| Copyright Year | 2008 |
| Description | Author affiliation: Xi'an Microelectron. Technol. Inst., Xi'an (Xinjian Zheng; Yiwei Zhang) |
| Abstract | To improve the DPA resistance of cryptographic device in intellectual cards, a power analysis platform is constructed for AES. After analyzed the AES encrypt process, a MASK circuit, disturbance circuit for clock and disturbance circuit for power are designed and implemented in an AES coprocessor of ZTEIC Corporation's intellectual card. The AES coprocessor can process data with 900 Mbps at 100 MHz frequency. The DPA test result shows the proportion of best DPA results is less than 5%, and with mask information. The AES coprocessor can defend DPA better than other products with a higher throughput. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 268734 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424421077 |
| DOI | 10.1109/WiCom.2008.1087 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-10-12 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Energy consumption Power measurement Frequency Throughput Microelectronics Cryptography Circuit testing Coprocessors Clocks Information analysis |
| Content Type | Text |
| Resource Type | Article |
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