NDLI: Implementation of an Embedded GPS Receiver Based on FPGA and MicroBlaze

Content Provider	IEEE Xplore Digital Library
Author	Ershen Wang Shufang Zhang Qing Hu Jiang Yi Xiaowen Sun
Copyright Year	2008
Description	Author affiliation: Sch. of Electron. Eng. & Comput. Sci., Dalian Maritime Univ., Dalian (Ershen Wang; Shufang Zhang; Qing Hu; Jiang Yi; Xiaowen Sun)
Abstract	A GPS receiver based on FPGA and MicroBlaze was developed. This kind of GPS receiver is made up of a RF Front- End and FPGA, with NemeriX NJ1006A and Xilinx XC2VP30 as its core chips. The RF Front-End chip NJ1006A receives the GPS signal and converts it to IF signal which is transfered to FPGA .The correlators array , C/A code generator,C/A code DCO and carrier DCO were analyzed and designed with Verilog hardware description language on FPGA. The algorithm of acquisition and tracking of GPS signal were discussed and implemented with MicroBlaze soft processor core in XC2VP30 . Meanwhile, the MicroBlaze soft processor core is responsible for communicating with FPGA user logic via the interface named OPB Bus. A parallel correlator using three local replica C/A code was developed and implemented on this FPGA-based GPS receiver, which improved the acquiring efficiency and accuracy of the GPS receiver. The simulation and verification results of the algorithm of GPS receiver are provided. The results demonstrated that the availability and reliability of this kind of design scheme of GPS receiver works well.
Starting Page	1
Ending Page	4
File Size	187222
Page Count	4
File Format	PDF
ISBN	9781424421077
DOI	10.1109/WiCom.2008.335
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-12
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Radio frequency RF signals Signal processing Signal generators Correlators Hardware design languages Signal analysis Field programmable gate arrays Signal design Global Positioning System
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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