NDLI: DPA Resistant AES on FPGA Using Partial DDL

Content Provider	IEEE Xplore Digital Library
Author	Kaps, J.-P. Velegalati, R.
Copyright Year	2010
Abstract	Current techniques to implement Dynamic Differential Logic (DDL), a countermeasure against Differential Power Analysis (DPA) on Field Programmable Gate Arrays (FPGAs) lead to an increase in area consumption of up to factor 11. In this paper we introduce Partial DDL, a technique in which DDL is applied only to a part of the cryptographic hardware implementation. We propose principle rules for Partial DDL to guide the designer in how to split up a circuit into DDL protected and unprotected paths. In order to validate our approach we implemented a lightweight architecture of AES in the Partial Separated Dynamic Differential Logic (Partial SDDL) for FPGAs. The results show that our implementation with Partial SDDL is as resistant to DPA as a full SDDL implementation while it consumes only 76% of the total area occupied by the full SDDL design. This is an area increase of 2.3 times over an unprotected single ended design.
Starting Page	273
Ending Page	280
File Size	286461
Page Count	8
File Format	PDF
ISBN	9780769540566
e-ISBN	9781424471430
DOI	10.1109/FCCM.2010.49
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Cryptography Circuit testing Protection Programmable logic arrays Wireless sensor networks Energy consumption Switches Registers Logic design Partial DDL DPA SDDL AES
Content Type	Text
Resource Type	Article

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