NDLI: Advanced Encryption Standard (AES) implementation with increased DPA resistance and low overhead

Content Provider	IEEE Xplore Digital Library
Author	Goodwin, J. Wilson, P.R.
Copyright Year	2008
Abstract	The use of the Advanced Encryption Standard (AES) has become pervasive in a large number of communication applications. The hardware to implement AES is non trivial and as a result it has a significant overhead in its raw form. Despite the algorithm being inherently secure, side channel attacks have exposed potential weaknesses via the implementation route, particularly power analysis. As a result, much effort has been expended in identifying techniques to mask the power signature that can give away the secret key. Unfortunately, the hardware overhead is usually a significant proportion of the size of the original algorithm and in addition, the key can sometimes still be ascertained due to manufacturing differences (such as track lengths) still delivering aspects of the key in a power signature. This paper describes an approach that requires a simple modification to the implementation of the AES algorithm, without altering its basic characteristics, which provides a significantly improved strength against side channel attacks with a minimal additional hardware overhead.
Starting Page	3286
Ending Page	3289
File Size	140814
Page Count	4
File Format	PDF
ISBN	9781424416837
DOI	10.1109/ISCAS.2008.4542160
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Cryptography Hardware Energy consumption Communication standards Algorithm design and analysis Protection Standards development Polynomials Manufacturing Throughput AES DPA Countermeasure
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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