NDLI: Stress evaluations in micro bump structures of FCBGA

Content Provider	IEEE Xplore Digital Library
Author	Wan Yu Huang Chen, E. Don San Jiang Yu Po Wang Chiang, J. Fang Lin Tsai Huang, R. Lee, E. Chang, I.
Copyright Year	2009
Description	Author affiliation: R&D Division, Siliconware Precision Industries Co. Ltd., 123, Sec 3 Da-Fong Road, Tantzu, Taichung, Taiwan (Wan Yu Huang; Chen, E.; Don San Jiang; Yu Po Wang; Chiang, J.; Fang Lin Tsai; Huang, R.; Lee, E.; Chang, I.)
Abstract	System in Package(SiP) includes technologies of Multi-chip Module(MCM), Multi-chip Package(MCP), stacked die, Package on Package(PoP), Package in Package(PiP) and Embedded substrate. While Au wire bonding technology is commonly used as current SIP interconnection solution, take Staked Die structure for example, with increasing stack die number the upper die needs longer wire bonding length for signal interconnection and results in lower electrical performance for whole system. In addition, wire bonding technology as Stacked die solution requires spacer die insertion between functional chips for bonding space and thus increases total package thickness. In order to achieve better electrical performance and reduce form factor, a new fine pitch bump technology of “Micro Bump” structure is developed with metal bump for both top and bottom chips. Micro bump structure is one of the key technologies of Trough Silicon Vias (TSV) and is used in chip to chip interconnection with the dimension of Micro bump smaller than typical flip chip bump.
Starting Page	140
Ending Page	143
File Size	1829263
Page Count	4
File Format	PDF
ISBN	9781424443413
DOI	10.1109/IMPACT.2009.5382160
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-21
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Gold Space technology Packaging Silicon Wire Flip chip Finite element methods Bonding Through-silicon vias Stress
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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