NDLI: Design of Readout Circuits Used for Micro-machined Capacitive Accelerometer

Content Provider	IEEE Xplore Digital Library
Author	Xiaowei Liu Haifeng Zhang Guangming Li Weiping Chen Xilian Wang
Copyright Year	2007
Description	Author affiliation: MEMS Center, Harbin Inst. of Technol. (Xiaowei Liu; Haifeng Zhang; Guangming Li; Weiping Chen; Xilian Wang)
Abstract	This paper describes a closed-loop micro-machined accelerometer implemented in a bulk-micromachining technology with integrated CMOS circuit. The operational principle of accelerometer is detailed. We establish a mathematical model of closed-loop system to compare the performance with the open accelerometer. Electrostatic force is served as a negative feedback in closed-loop operating mode to improve the bandwidth, linearity and dynamic range of micro-machined capacitive accelerometer. The noise source affected readout circuit is discussed to optimize circuit structure. The circuit is simulated using Hspice. The result of the circuit simulation shows good sensitivity and low power consumption. The sensor is designed to measure plusmn5g acceleration. Device sensitivity is larger than 15mV/g.
Starting Page	537
Ending Page	541
File Size	4567342
Page Count	5
File Format	PDF
ISBN	1424406102
DOI	10.1109/NEMS.2007.352076
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-16
Publisher Place	Thailand
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Accelerometers CMOS technology Circuit simulation Integrated circuit technology Mathematical model Electrostatics Force feedback Negative feedback Bandwidth Linearity noise Accelerometer Capacitive Sensing CMOS Interface circuit
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in