NDLI: Data-driven self-timed RSFQ digital integrated circuit and system

Content Provider	IEEE Xplore Digital Library
Author	Deng, Z.J. Yoshikawa, N. Whiteley, S.R. Van Duzer, T.
Copyright Year	2002
Abstract	A novel asynchronous timing scheme, data-driven self-timing (DDST) is proposed and implemented in Rapid Single-Flux-Quantum (RSFQ) superconductive integrated circuits. In this asynchronous approach, the timing signals are generated from the data and no global clock is needed to drive the RSFQ circuit and system. The essence of the self-timing scheme is to localize the system timing in order to avoid the overhead of global clock distribution, and to minimize the timing uncertainty. The DDST scheme has been applied to the design of a shift register, a demultiplexor, and a self-timed high speed digital test system. In this paper, test results of a 4-bit DDST shift register and a high speed on-chip clock generator will be presented to demonstrate the successful DDST operation of RSFQ integrated circuits at a rate of 20 Gb/s.
Sponsorship	Council on Superconductivity Appl. Superconductivity Conference Inc MIT
Starting Page	3634
Ending Page	3637
Page Count	4
File Size	778621
File Format	PDF
ISSN	10518223
Volume Number	7
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital integrated circuits Timing Clocks Circuit testing Shift registers Superconductivity Superconducting integrated circuits Signal generators Circuits and systems Uncertainty
Content Type	Text
Resource Type	Article
Subject	Condensed Matter Physics Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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