NDLI: Dynamic Circuit Analysis and Testing for International Space Station Science Experiments

Content Provider	IEEE Xplore Digital Library
Author	Hoang, H. Fu, S.J.
Copyright Year	2006
Description	Author affiliation: Boeing Co., Houston, TX (Hoang, H.)
Abstract	The International Space Station (ISS) Payload Engineering Integration (PEI) organization has developed the critical capabilities in dynamic circuit modeling and simulation to analyze electrical system anomalies during testing and operation. This presentation provides an example of the processes, tools and analytical techniques applied to the improvement of science experiments over-voltage clamp circuit design which is widely used by ISS science experiments. The voltage clamp circuit of Science Rack exhibits parasitic oscillations when a voltage spike couples to the field-effect transistor (FET) in the clamp circuit. The oscillation can cause partial or full conduction of the shunt FET in the circuit and may result in the destruction of the FET. In addition, the voltage clamp circuit is not designed to detect the high current through the FET, and this condition can result in damage to surrounding devices. The potential oscillation and the potential over-current, which could result in the destruction of the FET and surrounding devices, were analyzed by dynamic circuit simulation and tests. Test results show that the clamp circuit is highly susceptible to the false turn-on and parasitic oscillation when a voltage spike is coupled to the gate through the gate-to-drain capacitance or the diode capacitance. Circuit component analysis, based on FET parasitic inductance and capacitance, indicates that the frequency of parasitic oscillation falls in the range of 65 MHz to 80 MHz. The test results also show that a 100 ohms resistor in series with the FET gate eliminates parasitic oscillation while limiting the charging current at turn-on. Additionally, modeling results show that if the voltage is clamped, the FET current may exceed the operating region defined by the FET manufacturer, International Rectifier. This dynamic modeling provides essential design information for the set points of the current to flow through the FET. Engineering experience with power FET circuits has shown that they are prone to spurious activation if the circuit does not provide adequate damping. False turn-on of the FET circuit may cause sustained oscillations and damage the circuit. The test results and analytical models discussed in this paper reveals that parasitic oscillations can be effectively eliminated with a series resistor on the gate circuit of FET and this should be included as an important design consideration for the electrical power distribution circuits
Starting Page	1371
Ending Page	1378
File Size	500881
Page Count	8
File Format	PDF
ISBN	0780395247
ISSN	10879870
DOI	10.1109/ITHERM.2006.1645505
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Circuit analysis International Space Station FETs Clamps Voltage Parasitic capacitance Analytical models Circuit simulation Coupling circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Transimpedance crystal oscillator

Transistor-level CMOS gate models for timing analysis and simulation

A 3D analysis of source/drain capacitance in SOI MOSFET for practical circuit design

Extraction of circuit models for substrate cross-talk

Interconnect noise analysis for megabit DRAMs

A subnanosecond clamped-bit-line sense amplifier for 1T dynamic RAMs

Designing HV active clamps for HBM robustness

Extension of the MOSART circuit simulator to the analysis of BiCMOS circuits

Analysis and optimization of series-gated CML bipolar circuits

Dynamic Circuit Analysis and Testing for International Space Station Science Experiments

Similar Documents

Transimpedance crystal oscillator

Transistor-level CMOS gate models for timing analysis and simulation

A 3D analysis of source/drain capacitance in SOI MOSFET for practical circuit design

Extraction of circuit models for substrate cross-talk

Interconnect noise analysis for megabit DRAMs

A subnanosecond clamped-bit-line sense amplifier for 1T dynamic RAMs

Designing HV active clamps for HBM robustness

Extension of the MOSART circuit simulator to the analysis of BiCMOS circuits

Analysis and optimization of series-gated CML bipolar circuits

Dynamic Circuit Analysis and Testing for International Space Station Science Experiments