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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Smedes, T. van der Meijs, N.P. van Genderen, A.J. |
| Copyright Year | 1997 |
| Description | Author affiliation: Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands (Smedes, T.; van der Meijs, N.P.; van Genderen, A.J.) |
| Abstract | An increasingly urgent topic for the realization of densely packed (mixed signal) integrated circuits is prevention of cross-talk via the substrate. The paper proposes a boundary element method (BEM) for calculating an admittance matrix for the substrate in order to analyze the parasitic coupling during layout verification. In contrast to standard BE methods, we propose a Green's function which is specific to the domain and the problem. This allows minimal discretization and a direct extraction of circuit models for the cross-talk. The extraction can be combined with an efficient model reduction technique to obtain more simple, yet accurate models for the cross-talk. The complete extraction process has a linear time complexity and a constant memory usage. The method is fully implemented and integrated in an existing layout-to-circuit extractor. |
| Starting Page | 199 |
| Ending Page | 206 |
| File Size | 812572 |
| Page Count | 8 |
| File Format | |
| ISBN | 0818682000 |
| ISSN | 10636757 |
| DOI | 10.1109/ICCAD.1995.480013 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1995-11-05 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Coupling circuits Boundary element methods Integrated circuit interconnections Parasitic capacitance Mixed analog digital integrated circuits Design automation Numerical analysis Analytical models Circuit simulation Integrated circuit technology |
| Content Type | Text |
| Resource Type | Article |
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