NDLI: Almost every wire is removable: A modeling and solution for removing any circuit wire

Content Provider	IEEE Xplore Digital Library
Author	Xiaoqing Yang Tak-Kei Lam Wai-Chung Tang Yu-Liang Wu
Copyright Year	2012
Description	Author affiliation: Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong (Xiaoqing Yang; Tak-Kei Lam; Wai-Chung Tang; Yu-Liang Wu)
Abstract	Rewiring is a flexible and useful logic transformation technique through which a target wire can be removed by adding its alternative logics without changing the circuit functionality. In today's deep sub-micron era, circuit wires have become a dominating factor in most EDA processes and there are situations where removing a certain set of (perhaps extremely unwanted) wires is very useful. However, it has been experimentally suggested that the rewiring rate (percentage of original circuit wires being removable by rewiring) is only 30 to 40 % for optimized circuits in the past. In this paper, we propose a generalized error cancellation modeling and flow to show that theoretically almost every circuit wire is removable under this flow. In the Flow graph Error Cancellation based Rewiring (FECR) scheme we propose here, a rewiring rate of 95% of even optimized circuits is obtainable under this scheme, affirming the basic claim of this paper. To our knowledge, this is the first known rewiring scheme being able to achieve this near complete rewiring rate. Consequently, this wire-removal process can now be considered as a powerful atomic and universal operation for logic transformations, as virtually every circuit node can also be removed through repetitions of this rewiring process. Besides, this modeling can also serve as a general framework containing many other rewiring techniques as its special cases.
Starting Page	1573
Ending Page	1578
File Size	490349
Page Count	6
File Format	PDF
ISBN	9781457721458
ISSN	15301591
DOI	10.1109/DATE.2012.6176723
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-12
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Wires Vectors Circuit faults Testing Logic gates Flow graphs Integrated circuit modeling
Content Type	Text
Resource Type	Article

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