NDLI: Architecting a common-source-line array for bipolar non-volatile memory devices

Content Provider	IEEE Xplore Digital Library
Author	Bo Zhao Jun Yang Youtao Zhang Yiran Chen Hai Li
Copyright Year	2012
Description	Author affiliation: Dept. of ECE, University of Pittsburgh, USA (Bo Zhao; Jun Yang; Yiran Chen) \|\| Dept. of ECE, Polytechnic Inst. of NYU, USA (Hai Li) \|\| Dept. of CS, University of Pittsburgh, USA (Youtao Zhang)
Abstract	Traditional array organization of bipolar non-volatile memories such as STT-MRAM and memristor utilizes two bitlines for cell manipulations. With technology scaling, such bitline pair will soon become the bottleneck of density improvement. In this paper we propose a novel common-source-line array architecture, which uses a shared source-line along the row, leaving only one bitline per column. We also elaborate our design flow towards a reliable common-source-line array design, and demonstrate its effectiveness on STT-MRAM and memristor memory arrays. Our study results show that with comparable latency and energy, the proposed common-source-line array can save 33% and 21.8% area for Memristor-RAM and STT-MRAM respectively, comparing with corresponding traditional dual-bitline array designs.
Starting Page	1451
Ending Page	1454
File Size	1563231
Page Count	4
File Format	PDF
ISBN	9781457721458
ISSN	15301591
DOI	10.1109/DATE.2012.6176594
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-12
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Arrays Microprocessors Resistance Memristors Metals Reliability
Content Type	Text
Resource Type	Article

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