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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yibo Chen Guangyu Sun Qiaosha Zou Yuan Xie |
| Copyright Year | 2012 |
| Description | Author affiliation: Pennsylvania State University, University Park, 16802, USA (Qiaosha Zou; Yuan Xie) || Synopsys Inc., Mountain View, CA 94043, USA (Yibo Chen) || Peking University, Beijing, China 100084 (Guangyu Sun) |
| Abstract | Three-dimensional (3D) circuit integration is a promising technology to alleviate performance and power related issues raised by interconnects in nanometer CMOS. Physical planning of three-dimensional integrated circuits is substantially different from that of traditional planar integrated circuits, due to the presence of multiple layers of dies. To realize the full potential offered by three-dimensional integration, it is necessary to take physical information into consideration at higher-levels of the design abstraction for 3D ICs. This paper proposes an incremental system-level synthesis framework that tightly integrates behavioral synthesis of modules into the layer assignment and floorplan- ning stage of 3D IC design. Behavioral synthesis is implemented as a sub-routine to be called to adjust delay/power/variability/area of circuit modules during the physical planning process. Experimental results show that with the proposed synthesis-during-planning methodology, the overall timing yield is improved by 8%, and the chip peak temperature reduced by 6.6 °C, compared to the conventional planning-after-synthesis approach. |
| Starting Page | 1185 |
| Ending Page | 1190 |
| File Size | 1142960 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781457721458 |
| ISSN | 15301591 |
| DOI | 10.1109/DATE.2012.6176673 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-03-12 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Three dimensional displays Lead Integrated circuits Delay |
| Content Type | Text |
| Resource Type | Article |
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