NDLI: A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels

Content Provider	IEEE Xplore Digital Library
Author	Zhiliang Qian Ying Fei Teh Chi-Ying Tsui
Copyright Year	2012
Description	Author affiliation: VLSI Research Laboratory, Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, China (Zhiliang Qian; Ying Fei Teh; Chi-Ying Tsui)
Abstract	In this work, we propose a flit-level speedup scheme to enhance the network-on-chip(NoC) performance utilizing bidirectional channels. In addition to the traditional efforts on allowing flits of different packets using the idling internal and external bandwidth of the bi-directional channel, our proposed flit-level speedup scheme also allows flits within the same packet to be transmitted simultaneously on the bi-directional channel. For inter-router transmission, a novel distributed channel configuration protocol is developed to dynamically control the link directions. For the intra-router transmission, an input buffer architecture which supports reading and writing two flits from the same virtual channel at the same time is proposed. The switch allocator is also designed to support flit-level parallel arbitration. Simulation results on both synthetic traffic and real benchmarks show performance improvement in throughput and latency over the existing architectures using bi-directional channels.
Starting Page	1295
Ending Page	1300
File Size	1457668
Page Count	6
File Format	PDF
ISBN	9781457721458
ISSN	15301591
DOI	10.1109/DATE.2012.6176692
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-12
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Switches Bandwidth Resource management Routing Bidirectional control Benchmark testing Writing NoC Bidirectional channel flit-level speedup
Content Type	Text
Resource Type	Article

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