NDLI: Automated construction of a cycle-approximate transaction level model of a memory controller

Content Provider	IEEE Xplore Digital Library
Author	Todorov, V. Mueller-Gritschneder, D. Reinig, H. Schlichtmann, U.
Copyright Year	2012
Description	Author affiliation: Intel Mobile Communications GmbH, Germany (Todorov, V.; Reinig, H.) \|\| Technische Universität München, Germany (Mueller-Gritschneder, D.; Schlichtmann, U.)
Abstract	Transaction level (TL) models are key to early design exploration, performance estimation and virtual prototyping. Their speed and accuracy enable early and rapid System-on-Chip (SoC) design evaluation and software development. Most devices have only register transfer level (RTL) models that are too complex for SoC simulation. Abstracting these models to TL ones, however, is a challenging task, especially when the RTL description is too obscure or not accessible. This work presents a methodology for automatically creating a TL model of an RTL memory controller component. The device is treated as a black box and a multitude of simulations is used to obtain results, showing its timing behavior. The results are classified into conditional probability distributions, which are reused within a TL model to approximate the RTL timing behavior. The presented method is very fast and highly accurate. The resulting TL model executes approximately 1200 times faster, with a maximum measured average timing offset error of 7.66%.
Starting Page	1066
Ending Page	1071
File Size	1341641
Page Count	6
File Format	PDF
ISBN	9781457721458
ISSN	15301591
DOI	10.1109/DATE.2012.6176653
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-12
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Load modeling
Content Type	Text
Resource Type	Article

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