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2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Table of contents

DATE12 sponsors

DATE Executive Committee

DATE Sponsor Committee

Technical programme topic chairs

Technical programme committee

Best paper awards

EDAA/ACM SIGDA PhD forum at DATE 2012 in Dresden

$DATE^{13}$ Conference and Exhibition: March 18-22, 2013, Alpexpo, Grenoble, France - Call for Papers

The mobile society - chances and challenges for micro- and power electronics

New foundry models - accelerations in transformations of the semiconductor industry

Automated generation of directed tests for transition coverage in cache coherence protocols

On ESL verification of memory consistency for system-on-chip multiprocessing

Generating instruction streams using abstract CSP

A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture

A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems

CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory

TagTM - accelerating STMs with hardware tags for fast meta-data access

Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design

DRAM selection and configuration for real-time mobile systems

Using timing analysis for the design of future switched based Ethernet automotive networks

Fair energy resource allocation by minority game algorithm for smart buildings

On demand dependent deactivation of automotive ECUs

Smart power unit with ultra low power radio trigger capabilities for wireless sensor networks

IR-drop analysis of graphene-based power distribution networks

Off-path leakage power aware routing for SRAM-based FPGAs

Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization

Post-synthesis leakage power minimization

Fast and lightweight support for nested parallelism on cluster-based embedded many-cores

A divide and conquer based distributed run-time mapping methodology for many-core platforms

Dual Greedy: Adaptive garbage collection for page-mapping solid-state disks

EDA solutions to new-defect detection in advanced process technologies

Beyond CMOS - benchmarking for future technologies

Accurately timed transaction level models for virtual prototyping at high abstraction level

Out-of-order parallel simulation for ESL design

A probabilistic analysis method for functional qualification under Mutation Analysis

Approximating checkers for simulation acceleration

Guidelines for model based systems engineering

SURF algorithm in FPGA: A novel architecture for high demanding industrial applications

NOCEVE: Network on chip emulation and verification environment

Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks

Challenges in verifying an integrated 3D design

Multiple-source and multiple-destination charge migration in hybrid electrical energy storage systems

Benefits of green energy and proportionality in high speed wide area networks connecting data centers

Quantifying the impact of frequency scaling on the energy efficiency of the single-chip cloud computer

Neighbor-aware dynamic thermal management for multi-core platform

PANEL: Key challenges for the next generation of computing systems taming the data deluge

Playing games with scenario- and resource-aware SDF graphs through policy iteration

Verifying timing synchronization constraints in distributed embedded architectures

Task implementation of synchronous finite state machines

Enabling dynamic assertion-based verification of embedded software through model-driven design

NBTI mitigation by optimized NOP assignment and insertion

An accurate Single Event Effect digital design flow for reliable system level design

Cross entropy minimization for efficient estimation of SRAM failure rate

Experimentally driven verification of synthetic biological circuits

Genetic/bio design automation for (re-)engineering biological systems

Fast cycle estimation methodology for instruction-level emulator

Verification coverage of embedded multicore applications

Hazard driven test generation for SMT processors

Extending the lifetime of NAND flash memory by salvaging bad blocks

A case study on the application of real phase-change RAM to main memory subsystem

A high-performance dense block matching solution for automotive 6D-vision

Optimization intensive energy harvesting

Designing FlexRay-based automotive architectures: A holistic OEM approach

Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems

VaMV: Variability-aware Memory Virtualization

Hybrid simulation for extensible processor cores

Leveraging reconfigurability to raise productivity in FPGA functional debug

MOUSSE: Scaling modelling and verification to complex Heterogeneous Embedded Systems evolution

Run-time power-gating in caches of GPUs for leakage energy savings

Automatic generation of functional models for embedded processor extensions

An integrated test generation tool for enhanced coverage of Simulink/Stateflow models

Model driven resource usage simulation for critical embedded systems

RAG: An efficient reliability analysis of logic circuits on graphics processing units

CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks

An MILP-based aging-aware routing algorithm for NoCs

AFRA: A low cost high performance reliable routing for 3D mesh NoCs

Middleware services for network interoperability in smart energy efficient buildings

Low-power embedded system for real-time correction of fish-eye automotive cameras

Mechatronic system for energy efficiency in bus transport

Intelligent and collaborative embedded computing in automation engineering

Variation-aware leakage power model extraction for system-level hierarchical power analysis

Runtime power estimator calibration for high-performance microprocessors

Estimation based power and supply voltage management for future RF-powered multi-core smart cards

Application-specific memory partitioning for joint energy and lifetime optimization

State-of-the-art tools and techniques for quantitative modeling and analysis of embedded systems

Hybrid source-level simulation of data caches using abstract cache models

Accurate source-level simulation of embedded software with respect to compiler optimizations

Scheduling for register file energy minimization in explicit datapath architectures

Multi-objective aware extraction of task-level parallelism using genetic algorithms

RTL analysis and modifications for improving at-speed test

Test generation for clock-domain crossing faults in integrated circuits

A new SBST algorithm for testing the register file of VLIW processors

On the optimality of K longest path generation algorithm under memory constraints

Embedded systems and software challenges in electric vehicles

Accelerators and emulators: Can they become the platform of choice for hardware verification?

A closed-loop system for artifact mitigation in ambulatory electrocardiogram monitoring

Enabling advanced inference on sensor nodes through direct use of compressively-sensed signals

A multi-parameter bio-electric ASIC sensor with integrated 2-wire data transmission protocol for wearable healthcare system

Energy-efficient branch prediction with Compiler-guided History Stack

Toward virtualizing branch direction prediction

S/DC: A storage and energy efficient data prefetcher

An architecture-level approach for mitigating the impact of process variations on extensible processors

PCASA: Probabilistic control-adjusted Selective Allocation for shared caches

Dynamic Directories: A mechanism for reducing on-chip interconnect power in multicores

Dynamic cache management in multi-core architectures through run-time adaptation

Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs

Preemption delay analysis for floating non-preemptive region scheduling

Harmonic semi-partitioned scheduling for fixed-priority real-time tasks on multi-core platform

Static scheduling of a Time-Triggered Network-on-Chip based on SMT solving

Formal analysis of sporadic overload in real-time systems

Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis

Modeling and testing of interference faults in the nano NAND Flash memory

Impact of resistive-open defects on the heat current of TAS-MRAM architectures

Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling

Dynamic-priority arbiter and multiplexer soft macros for on-chip networks switches

Low power aging-aware register file design by duty cycle balancing

PowerAdviser: An RTL power platform for interactive sequential optimizations

Towards parallel execution of IEC 61131 industrial cyber-physical systems applications

A scan pattern debugger for partial scan industrial designs

FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs

Exploiting binary translation for fast ASIP design space exploration on FPGAs

Design of a low-energy data processing architecture for WSN nodes

Application-specific power-efficient approach for reducing register file vulnerability

On-line scheduling of target sensitive periodic tasks with the gravitational task model

Online scheduling for multi-core shared reconfigurable fabric

SCFIT: A FPGA-based fault injection technique for SEU fault model

Research and innovation on Advanced Computing - an EU perspective

E-MOBILITY PANEL - role of EDA in the development of electric vehicles

Memristor technology in future electronic system design

TempoMP: Integrated prediction and management of temperature in heterogeneous MPSoCs

Thermal balancing of liquid-cooled 3D-MPSoCs using channel modulation

Statistical thermal modeling and optimization considering leakage power variations

Analysis and runtime management of 3D systems with stacked DRAM for boosting energy efficiency

A guiding coverage metric for formal verification

Verification of partial designs using incremental QBF solving

Non-solution implications using reverse domination in a modern SAT-based debugging environment

Optimizing performance analysis for synchronous dataflow graphs with shared resources

Compositional system-level design exploration with planning of high-level synthesis

Correct-by-construction multi-component SoC design

Model checking of Scenario-Aware Dataflow with CADP

An instruction scratchpad memory allocation for the precision timed architecture

Bounding WCET of applications using SDRAM with Priority Based Budget Scheduling in MPSoCs

Time analysable synchronisation techniques for parallelised hard real-time applications

Design for test and reliability in ultimate CMOS

Optimal energy management and recovery for FEV

Virtual platforms: Breaking new grounds

An FPGA-based accelerator for cortical object classification

Power-efficient error-resiliency for H.264/AVC Context-Adaptive Variable Length Coding

Towards accurate hardware stereo correspondence: A real-time FPGA implementation of a segmentation-based adaptive support weight algorithm

An FPGA-based parallel processor for Black-Scholes option pricing using finite differences schemes

A SAT-based fitness function for evolutionary optimization of polymorphic circuits

Mach-Zehnder interferometer based design of all optical reversible binary adder

Weighted area technique for electromechanically enabled logic computation with cantilever-based NEMS switches

Response-surface-based design space exploration and optimisation of wireless sensor nodes with tunable energy harvesters

Holistic modeling of embedded systems with multi-discipline feedback: Application to a Precollision Mitigation Braking System

Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selection

A fast analog circuit yield estimation method for medium and high dimensional problems

Fast isomorphism testing for a graph-based analog circuit synthesis framework

Design of streaming applications on MPSoCs using abstract clocks

SPDF: A schedulable parametric data-flow MoC

Modeling static-order schedules in synchronous dataflow graphs

Design space pruning through hybrid analysis in system-level design space exploration

Test pin count reduction for NoC-based Test delivery in multicore SOCs

On effective TSV repair for 3D-stacked ICs

DfT schemes for resistive open defects in RRAMs

Timing Modeling with AUTOSAR - Current state and future directions

Challenges and new trends in probabilistic timing analysis

QBf-based boolean function bi-decomposition

Automatic transition between structural system views in a safety relevant embedded systems development process

Towards new applications of multi-function logic: Image multi-filtering

Memory-map selection for firm real-time SDRAM controllers

Real-time implementation and performance optimization of 3D sound localization on GPUs

Impact of TSV area on the dynamic range and frame rate performance of 3D-integrated image sensors

Minimizing the latency of quantum circuits during mapping to the ion-trap circuit fabric

Voltage propagation method for 3-D power grid analysis

Yield optimization for radio frequency receiver at system level

Parallel statistical analysis of analog circuits by GPU-accelerated graph-based approach

Automated critical device identification for configurable analogue transistors

Analysis of multi-domain scenarios for optimized dynamic power management strategies

PUF-based secure test wrapper design for cryptographic SoC testing

Complexity, quality and robustness - the challenges of tomorrow's automotive electronics

Measuring and improving the robustness of automotive smart power microelectronics

Panel: What is EDA doing for trailing edge technologies?

Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors

A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories

A resilient architecture for low latency communication in shared-L1 processor clusters

Performance-reliability tradeoff analysis for multithreaded applications

Efficient Gröbner basis reductions for formal verification of galois field multipliers

Scalable progress verification in credit-based flow-control systems

Formal methods for ranking counterexamples through assumption mining

Transistor-level gate model based statistical timing analysis considering correlations

Current source modeling for power and timing analysis at different supply voltages

Clock skew scheduling for timing speculation

Robust and flexible mapping for real-time distributed applications during the early design phases

A methodology for automated design of hard-real-time embedded streaming systems

Co-design techniques for distributed real-time embedded systems with communication security constraints

Logic encryption: A fault analysis perspective

Low-cost implementations of on-the-fly tests for random number generators

Post-deployment trust evaluation in wireless cryptographic ICs

Batteries and battery management systems for electric vehicles

Power management of multi-core chips: Challenges and pitfalls

P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator

Multi-core architecture design for ultra-low-power wearable health monitoring systems

Reducing the energy cost of computing through efficient co-scheduling of parallel workloads

SAFER PATH: Security architecture using fragmented execution and replication for protection against trojaned hardware

ASIC implementations of five SHA-3 finalists

Side channel analysis of the SHA-3 finalists

Combining module selection and replication for throughput-driven streaming programs

Exploiting area/delay tradeoffs in high-level synthesis

Predicting best design trade-offs: A case study in processor customization

Automatic design of low-power encoders using reversible circuit synthesis

Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM

Sliding-Mode Control to Compensate PVT Variations in dual core systems

MAPG: Memory access power gating

State of health aware charge management in hybrid electrical energy storage systems

Automated construction of a cycle-approximate transaction level model of a memory controller

Refinement of UML/MARTE models for the design of networked embedded systems

Debugging of inconsistent UML/OCL models

An analytical technique for characterization of transceiver IQ imbalances in the loop-back mode

Testing RF circuits with true non-intrusive built-in sensors

Monitoring active filters under automotive aging scenarios with embedded instrument

Analysis of instruction-level vulnerability to dynamic voltage and temperature variations

CrashTest'ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions

A hybrid HW-SW approach for intermittent error mitigation in streaming-based embedded systems

Probabilistic response time bound for CAN messages with arbitrary deadlines

Exploring pausible clocking based GALS design for 40-nm system integration

Static analysis of asynchronous clock domain crossings

A scalable GPU-based approach to accelerate the multiple-choice knapsack problem

Enhancing non-linear kernels by an optimized memory hierarchy in a High Level Synthesis flow

Workload-aware voltage regulator optimization for power efficient multi-core processors

An energy efficient DRAM subsystem for 3D integrated SoCs

Eliminating invariants in UML/OCL models

On-chip source synchronous interface timing test scheme with calibration

ITRS 2011 Analog EDA Challenges and Approaches

UWB: Innovative architectures enable disruptive low power wireless applications

Pathways to servers of the future

Amplitude demodulation-based EM analysis of different RSA implementations

RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs

Revealing side-channel issues of complex circuits by enhanced leakage models

3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs

Multi-token resource sharing for pipelined asynchronous systems

Design of low-complexity digital finite impulse response filters on FPGAs

An efficient framework for passive compact dynamical modeling of multiport linear systems

Analysis and design of sub-harmonically injection locked oscillators

Design of an intrinsically-linear double-VCO-based ADC with $2^{nd}-order$ noise shaping

Large signal simulation of integrated inductors on semi-conducting substrates

Time-triggered implementations of mixed-criticality automotive software

Timing analysis of cyber-physical applications for hybrid communication protocols

A cyberphysical synthesis approach for error recovery in digital microfluidic biochips

Predictive control of networked control systems over differentiated services lossy networks

Input vector monitoring on line concurrent BIST based on multilevel decoding logic

High performance reliable variable latency carry select addition

Salvaging chips with caches beyond repair

Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms

Moore meets maxwell

Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs

A TDM NoC supporting QoS, multicast, and fast connection set-up

Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC

A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels

Spintronic memristor based temperature sensor design with CMOS current reference

3D-FlashMap: A physical-location-aware block mapping strategy for 3D NAND flash memory

Asymmetry of MTJ switching and its implication to STT-RAM designs

Comparative analysis of SRAM memories used as PUF primitives

Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs

A sensor-assisted self-authentication framework for hardware trojan detection

Towards improving simulation of analog circuits using model order reduction

Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation

A GPU-accelerated envelope-following method for switching power converter simulation

Simulation of the steady state of oscillators in the time domain

Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique

State-based full predication for low power coarse-grained reconfigurable architecture

UPaRC—Ultra-fast power-aware reconfiguration controller

Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures

VLSI legalization with minimum perturbation by iterative augmentation

Agglomerative-based flip-flop merging with signal wirelength optimization

Fixed origin corner square inspection layout regularity metric

Programmability and performance portability aspects of heterogeneous multi-/manycore systems

Efficient variation-aware EM-semiconductor coupled solver for the TSV structures in 3D IC

Verifying jitter in an analog and mixed signal design using dynamic time warping

MEDS: Mockup Electronic Data Sheets for automated testing of cyber-physical systems using digital mockups

Component-based and aspect-oriented methodology and tool for Real-Time Embedded Control Systems Design

Cyber-physical cloud computing: The binding and migration problem

An adaptive approach for online fault management in many-core architectures

An hybrid architecture to detect transient faults in microprocessors: An experimental validation

Evaluation of a new RFID system performance monitoring approach

A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach

A block-level flash memory management scheme for reducing write activities in PCM-based embedded systems

Architecting a common-source-line array for bipolar non-volatile memory devices

Layout-aware optimization of stt mrams

Characterization of the bistable ring PUF

An operational matrix-based algorithm for simulating linear and fractional differential circuits

A flexible and fast software implementation of the FFT on the BPE platform

Hierarchical propagation of geometric constraints for full-custom physical design of ICs

Double-patterning friendly grid-based detailed routing with online conflict resolution

Design and analysis of via-configurable routing fabrics for structured ASICs

Towards a wireless medical smart card

A fast, source-synchronous ring-based network-on-chip design

Area efficient asynchronous SDM routers using 2-stage Clos switches

Power-efficient calibration and reconfiguration for on-chip optical communication

Modeling and design exploration of FBDRAM as on-chip memory

Bloom filter-based dynamic wear leveling for phase-change RAM

A compression-based area-efficient recovery architecture for nonvolatile processors

A Network-on-Chip-based turbo/LDPC decoder architecture

A complexity adaptive channel estimator for low power

A high performance split-radix FFT with constant geometry architecture

Selective flexibility: Breaking the rigidity of datapath merging

An out-of-order superscalar processor on FPGA: The ReOrder Buffer design

Partial online-synthesis for mixed-grained reconfigurable architectures

Congestion-aware scheduling for NoC-based reconfigurable systems

Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction

Almost every wire is removable: A modeling and solution for removing any circuit wire

Mapping into LUT structures

Row-shift decompositions for index generation functions

Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations

On effective flip-chip routing via pseudo single redistribution layer

AIR (Aerial Image Retargeting): A novel technique for in-fab automatic model-based retargeting-for-yield

Layout-Driven Robustness Analysis for misaligned Carbon Nanotubes in CNTFET-based standard cells

Advances in variation-aware modeling, verification, and testing of analog ICs

2011 Design, Automation & Test in Europe

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)

2009 Design, Automation & Test in Europe Conference & Exhibition

2008 Design, Automation and Test in Europe

2007 Design, Automation & Test in Europe Conference & Exhibition

Proceedings of the Design Automation & Test in Europe Conference

Design, Automation and Test in Europe

Proceedings Design, Automation and Test in Europe Conference and Exhibition

2003 Design, Automation and Test in Europe Conference and Exhibition

Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition

Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001

Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537)

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)

Proceedings Design, Automation and Test in Europe

Foreword

Content Provider	IEEE Xplore Digital Library
Author	Rosenstiel, Wolfgang Thiele, Lothar
Copyright Year	2012
Description	Author affiliation: University of Tuebingen and edacentrum, Germany (Rosenstiel, Wolfgang) \|\| ETH Zurich, Switzerland (Thiele, Lothar)
Abstract	We proudly present to you the Advance Programme of DATE 12. DATE combines the world's favourite electronic systems design and test conference with an international exhibition for electronic design, automation and test, from system level hardware and software implementation right down to integrated circuit design. While many conferences currently suffer from travel restrictions in many companies and face severe problems in attracting attendees, DATE 2012 received some 950 submissions. The boost in submissions by 37% and 18% in the Embedded Systems Software and the Applications Track reflects the key importance of software and applications for a wealthy economy and underlines the leading role of DATE in these fields. The importance of DATE as a worldwide indispensable meeting point is demonstrated by the fact that more than 50% of the submissions came from outside Europe. The most attractive topics this year were Simulation and Validation as well as Architectural and Microarchitectural Design.
File Size	110547
File Format	PDF
ISBN	9781457721458
ISSN	15301591
DOI	10.1109/DATE.2012.6176416
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-12
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Content Type	Text

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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