NDLI: An accurate Single Event Effect digital design flow for reliable system level design

Content Provider	IEEE Xplore Digital Library
Author	Pontes, J. Calazans, N. Vivet, P.
Copyright Year	2012
Description	Author affiliation: CEA-LETI, Grenoble, France (Vivet, P.) \|\| Faculty of Informatics - FACIN, - PUCRS, Porto Alegre, RS, Brazil (Pontes, J.; Calazans, N.)
Abstract	Similar to local variations and signal integrity problems, Single Event Effects (SEEs) are a new design concern for digital system design that arises in deep sub-micron technologies. In order to design reliable digital systems in such technologies, it is mandatory to precisely model and take into account SEEs. This paper proposes a new accurate design flow to model non-permanent SEE effects that can be applied at system level for reliable digital circuit design. Starting from low level SPICE-accurate simulations, SEEs are characterized, modeled and simulated in the digital design using commercial and well accepted standards and tools. The proposed design flow has been fully validated through a complete digital design, a cryptographic core implemented in a 32nm CMOS technology. Finally, using the SEE design flow, the paper presents some reliability impact analysis, both at standard cell level and design level.
Starting Page	224
Ending Page	229
File Size	546183
Page Count	6
File Format	PDF
ISBN	9781457721458
ISSN	15301591
DOI	10.1109/DATE.2012.6176466
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-12
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Timing Integrated circuit modeling Mathematical model Solid modeling Libraries Robustness Digital circuits radiation hardening Single event effects soft errors
Content Type	Text
Resource Type	Article

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