NDLI: Scheduling for register file energy minimization in explicit datapath architectures

Content Provider	IEEE Xplore Digital Library
Author	Dongrui She Yifan He Mesman, B. Corporaal, H.
Copyright Year	2012
Description	Author affiliation: Department of Electrical Engineering, Eindhoven University of Technology, The Netherland (Dongrui She; Yifan He; Mesman, B.; Corporaal, H.)
Abstract	In modern processor architectures, the register file (RF) consumes considerable amount of the processor power. It is well known that by allowing software to have explicit fine-grained control over the datapath, the transport-triggered architectures (TTAs) can substantially reduce the RF traffic, thereby minimizing the RF energy. However, it is important to make sure that the gain in RF is not cancelled out by the overhead due to the fine-grained datapath control, in particular, the deterioration of code density in conventional TTAs. In this paper, we analyze the potential of minimizing RF energy in MOVE-Pro, a TTA-based processor framework. We present a flexible compiler backend, which performs energy-aware instruction scheduling to push the limit of RF energy reduction. The experimental results show that with the proposed energy-aware compiler backend, MOVE-Pro is able to significantly reduce RF energy compared to its RISC/VLIW counterparts, by up to 80%. Meanwhile the code density of MOVE-Pro remains at the same level as its RISC/VLIW counterparts, allowing the energy saving in RF to be successfully transferred to total energy saving.
Starting Page	388
Ending Page	393
File Size	568029
Page Count	6
File Format	PDF
ISBN	9781457721458
ISSN	15301591
DOI	10.1109/DATE.2012.6176502
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-12
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Radio frequency Schedules Reduced instruction set computing Registers VLIW Energy consumption Kernel Register File TTA MOVE-Pro Low Power Code Generation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Scheduling for register file energy minimization in explicit datapath architectures

MOVE-Pro: A low power and high code density TTA architecture

OpenCL code generation for low energy wide SIMD architectures with explicit datapath

Register file port requirements of transport triggered architectures

Register File Energy Optimization for Snooping Based Clustered VLIW Architectures

Dynamic Operands Insertion for VLIW Architecture with a Reduced Bit-width Instruction Set

978-3-9810801-8-6/DATE12 / c�2012 EDAA Scheduling for Register File Energy Minimization in Explicit Datapath Architectures

Partitioned register file for TTAs

Code generation for a novel STA architecture by using post-processing backend

Scheduling for register file energy minimization in explicit datapath architectures

Similar Documents

Scheduling for register file energy minimization in explicit datapath architectures

MOVE-Pro: A low power and high code density TTA architecture

OpenCL code generation for low energy wide SIMD architectures with explicit datapath

Register file port requirements of transport triggered architectures

Register File Energy Optimization for Snooping Based Clustered VLIW Architectures

Dynamic Operands Insertion for VLIW Architecture with a Reduced Bit-width Instruction Set

978-3-9810801-8-6/DATE12 / c�2012 EDAA Scheduling for Register File Energy Minimization in Explicit Datapath Architectures

Partitioned register file for TTAs

Code generation for a novel STA architecture by using post-processing backend

Scheduling for register file energy minimization in explicit datapath architectures