NDLI: 3D-FlashMap: A physical-location-aware block mapping strategy for 3D NAND flash memory

Content Provider	IEEE Xplore Digital Library
Author	Yi Wang Bathen, L.A.D. Zili Shao Dutt, N.D.
Copyright Year	2012
Description	Author affiliation: Department of Computing, The Hong Kong Polytechnic University, Hung Hom, Kowloon, Hong Kong (Yi Wang; Zili Shao) \|\| Center for Embedded Computer Systems, University of California, Irvine, 92697, USA (Bathen, L.A.D.; Dutt, N.D.)
Abstract	Three-dimensional (3D) flash memory is emerging to fulfil the ever-increasing demands of storage capacity. In 3D NAND flash memory, multiple layers are stacked to increase bit density and reduce bit cost of flash memory. However, the physical architecture of 3D flash memory leads to a higher probability of disturbance to adjacent physical pages and greatly increases bit error rates. This paper presents 3D-FlashMap, a novel physical-location-aware block mapping strategy for three-dimensional NAND flash memory. 3D-FlashMap permutes the physical mapping of blocks and maximizes the distance between consecutively logical blocks, which can significantly reduce the disturbance to adjacent physical pages and effectively enhance the reliability. We apply 3D-FlashMap to a representative flash storage system. Experimental results show that the proposed scheme can reduce uncorrectable page errors by 85% with less than 2% space overhead in comparison with the baseline scheme.
Starting Page	1307
Ending Page	1312
File Size	281208
Page Count	6
File Format	PDF
ISBN	9781457721458
ISSN	15301591
DOI	10.1109/DATE.2012.6176694
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-12
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Ash Reliability Logic gates Three dimensional displays Resource management File systems Equations
Content Type	Text
Resource Type	Article

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