NDLI: NOCEVE: Network on chip emulation and verification environment

Content Provider	IEEE Xplore Digital Library
Author	Hammami, O. Xinyu Li Brault, J.-M.
Copyright Year	2012
Description	Author affiliation: EVE, 2 bis, Voie La Cardon, Parc Gutenberg, Batiment B, 91120 Palaiseau, FRANCE (Xinyu Li; Brault, J.-M.) \|\| ENSTA PARISTECH, 32 Bvd Victor, 75739, FRANCE (Hammami, O.)
Abstract	We present in this paper NOCEVE an industrial Network on Chip (NoC) emulation and verification environment on industrial large scale multi-FPGA emulation platform for billion cycle application. It helps designer to improve system performance by the analysis of traffic distribution and balance through the network on chip. The hardware monitoring network is generated by another commercial NoC design tool. It consists of traffic collectors, which is reconfigurable to collect different traffic information such as packet latency and throughput. The statistic traffic information is collected during real application execution on FPGA platform and it is sent through monitoring network on FPGA and then PCI bright board back to host computer for real-time visualization or post-execution data analysis. NOCEVE is the first industrial NoC emulation and verification environment for billion cycle applications.
Starting Page	163
Ending Page	164
File Size	531649
Page Count	2
File Format	PDF
ISBN	9781457721458
ISSN	15301591
DOI	10.1109/DATE.2012.6176452
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-12
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Monitoring Field programmable gate arrays Emulation Hardware System-on-a-chip Software Benchmark testing verification emulation FPGA NoC
Content Type	Text
Resource Type	Article

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