NDLI: Selective flexibility: Breaking the rigidity of datapath merging

Content Provider	IEEE Xplore Digital Library
Author	Stojilovic, M. Novo, D. Saranovac, L. Brisk, P. Ienne, P.
Copyright Year	2012
Description	Author affiliation: University of Belgrade, School of Electrical Engineering, Bulevar Kralja Aleksandra 73, 11120, Serbia (Saranovac, L.) \|\| University of California Riverside, Department of Computer Science and Engineering, 92521, U.S.A. (Brisk, P.) \|\| University of Belgrade, Institute Mihailo Pupin, Volgina 15, 11060, Serbia (Stojilovic, M.) \|\| École Polytechnique Fédérale de Lausanne (EPFL), School of Computer and Communication Sciences, CH-1015, Switzerland (Novo, D.; Ienne, P.)
Abstract	Hardware specialization is often the key to efficiency for programmable embedded systems, but comes at the expense of flexibility. This paper combines flexibility and efficiency in the design and synthesis of domain-specific datapaths. We merge all individual paths from the Data Flow Graphs (DFGs) of the target applications, leading to a minimal set of required resources; this set is organized into a column of physical operators and cloned, thus generating a domain-specific rectangular lattice. A bus-based FPGA-style interconnection network is then generated and dimensioned to meet the needs of the applications. Our results demonstrate that the lattice has good flexibility: DFGs that were not used as part of the datapath creation phase can be mapped onto it with high probability. Compared to an ASIC design of a single DFG, the speed of our domain-specific coarse-grained reconfigurable datapath is degraded by a factor up to 2×, compared to 3–4× for an FPGA; similarly, our lattice is up to 10× larger than an ASIC, compared to 20–40× for an FPGA. We estimate that our array is up to 6× larger than an ASIC accelerator, which is synthesized using datapath merging and has limited or null generality.
Starting Page	1543
Ending Page	1548
File Size	584824
Page Count	6
File Format	PDF
ISBN	9781457721458
ISSN	15301591
DOI	10.1109/DATE.2012.6176718
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-12
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Application specific integrated circuits Merging Field programmable gate arrays Arrays Delay Routing Educational institutions
Content Type	Text
Resource Type	Article

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